On a BRK instruction, the CPU does the same as in the IRQ case, but sets bit #4 (B flag) in the copy of the status register that is saved on the stack.
=== Half Cycles ===
The 6502 divides each clock cycle into two phases (ϕ1 and ϕ2):
* During the ϕ1 half-cycle, no bus access occurs. This phase is dedicated to internal CPU operations.
* During the ϕ2 half-cycle, if needed, the CPU accesses the external bus for memory reads/writes or I/O operations.
The use of half-cycles ensures that memory and I/O devices have predictable timing windows when the CPU will access the bus, while still allowing the CPU to perform internal operations in parallel.
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