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MOS 6502

266 bytes removed, 20:28, 3 September 2024
/* Oddities */
== Oddities ==
 
* The 6502 divides each clock cycle into two phases (ϕ1 and ϕ2). The use of half-cycles ensures that memory and I/O devices have predictable timing windows when the CPU will access the bus, while still allowing the CPU to perform internal operations in parallel.
* The decimal mode flag in the processor status register is unchanged following an interrupt of any kind. This behavior can potentially result in a difficult to locate bug in the interrupt handler if decimal mode happens to be enabled at the time of an interrupt.
Phi2x
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