Changes
/* IRQ / NMI / BRK / RESET */
The priority sequence for interrupts, from top priority to bottom, is as follows: RESET, BRK, NMI, IRQ. [https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf Source at chapter 7.19]
On NMOS, the simultaneous assertion of a hardware interrupt line and execution of BRK was not accounted for in the design — the BRK instruction will be ignored in such a case. On CMOS, this situation is correctly handled by executing BRK and then servicing the interrupt.
=== Half Cycles ===
