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CRTC

45 bytes removed, 00:40, 18 November 2024
/* PPI VSYNC */
The VSYNC pin of the CRTC is directly connected to bit0 of port B of the PPI. There is no delay involved.
In the CRTC CompendiumOn Amstrad CPC (not Plus!), chapter 7.3 "Fake VSYNC", [[Longshot]] has it is also experimented with reversing possible to reverse the direction of PPI port B to output a VSYNC signal directly from the PPI to the Gate Array, a technique called "Fake VSYNC". This technique is not for the faint of heart!
As an exception, the Ghost VSYNC of CRTC 2 overpowers the Fake VSYNC.
Phi2x
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