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CRTC

26 bytes removed, 02:12, 18 November 2024
/* PPI VSYNC */
The VSYNC pin of the CRTC is directly connected to bit0 of port B of the PPI. There is no delay involved.
On Amstrad CPC (not Plus!), it is also possible to reverse the direction of PPI port B to output a (fake) VSYNC signal directly from the PPI to the Gate Array, a technique called "Fake VSYNC".
As an exception, the Ghost VSYNC of CRTC 2 overpowers the Fake VSYNC.
Phi2x
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