== Hybrid 16/32‑Bit Design ==
The design implements a 32-bit instruction set, with 32-bit registers and a 16-bit data bus. The address bus is 24 bits and does not use memory segmentationwide; while internal address computations occur using 32‑bit arithmetic, which made it easier to program for..only the lower 24 bits are available on the physical pins. but this gave trouble with later CPU models as it was a common trick for programs to store data in the 4th byte of an address (which simply would be ignored).
Internally, it uses a 16-bit data arithmetic logic unit (ALU) and two more 16-bit ALUs used mostly for addresses.