Changes

The design implements a 32-bit instruction set, with 32-bit registers and a 16-bit data bus. The address bus is 24 bits wide; while internal address computations occur using 32‑bit arithmetic, only the lower 24 bits are available on the physical pins. but this gave trouble with later CPU models as it was a common trick for programs to store data in the 4th byte of an address (which simply would be ignored).

InternallyThe address bus is 24 bits wide; while internal address computations occur using 32‑bit arithmetic, it uses only the lower 24 bits are available on the physical pins. This design yields a flat memory model with a maximum addressable space of 16-bit MB without the complications of segmentation, simplifying both operating system design and application programming. But this gave trouble with later CPU models as it was a common trick for programs to store data arithmetic logic unit in the 4th byte of an address (ALUwhich simply would be ignored) and two more 16-bit ALUs used mostly for addresses.

Internally, it uses a 16-bit data arithmetic logic unit (ALU) and two more 16-bit ALUs used mostly for addresses. At one time, one 32-bit address and one 16-bit data calculation can take place within the MC68000. This speeds instruction execution time considerably by processing addresses and data in parallel.