Changes

* Opcode Fetch (aka M1 cycle): this is always the first (and sometimes only) machine cycle in an instruction (4 clock cyclesT-states)* Memory Read: read a byte from memory (3 clock cyclesT-states)* Memory Write: write a byte to memory (3 clock cyclesT-states)* IO Read: read a byte from an IO port (4 clock cyclesT-states)* IO Write: write a byte to an IO port (4 clock cyclesT-states)* Interrupt Acknowledge: these are special machine cycles M-cycle which are is executed at the start of maskable interrupt handling* Extra: many instructions contain extra clock cycles T-states necessary for computations. In the official CPU documentation, these are sometimes identified as a separate machine cyclesM-cycle, and sometimes just lumped together with other machine M-cycle types.For example:**The INC pp instruction is an example where the opcode has only one M-cycle, but consisting of 6 T-states instead of the usual 4.**The CALL cc,nn instruction is an example where has an extra clock cycle is inserted in M3 depending if cc is true or not.