**The instruction RST t has an M1 cycle consisting of 5 T-states instead of the usual 4.
**The CALL cc,nn instruction has an extra T-state inserted in M3 depending if cc is true or not.
<br>
== Timing Diagrams ==
<gallery>
File:Z80-machine-cycles.png|Basic CPU Timing
File:Z80-M1.png|Opcode Fetch
File:Z80-M2-M3.png|Memory Read or Write
File:Z80-interrupt.png|Interrupt Request
File:Z80-nmi.png|NMI Request
File:Z80-IO.png|Input or Output
File:Z80-bus.png|Bus Request
File:Z80-halt.png|HALT Exit
</gallery>
<br>
See: [https://www.righto.com/2014/10/how-z80s-registers-are-implemented-down.html How the Z80's registers are implemented] [https://www.righto.com/2013/11/the-z-80s-16-bit-incrementdecrement.html The 16-bit increment/decrement circuit] [https://www.righto.com/2013/09/the-z-80-has-4-bit-alu-heres-how-it.html The 4-bit ALU] [https://zeptobars.com/en/read/Zilog-Z80-Z0840004PSC Z80 die-shot (zeptobars)] [https://siliconpr0n.org/map/zilog/z0840008psc-z80cpu/bercovici_mz/ Z80 die-shot (bercovici)]
<br>
== Timing Diagrams ==
<gallery>
File:Z80-machine-cycles.png|Basic CPU Timing
File:Z80-M1.png|Opcode Fetch
File:Z80-M2-M3.png|Memory Read or Write
File:Z80-interrupt.png|Interrupt Request
File:Z80-nmi.png|NMI Request
File:Z80-IO.png|Input or Output
File:Z80-bus.png|Bus Request
File:Z80-halt.png|HALT Exit
</gallery>
<br>