Changes
/* Instruction Set */
{| class="wikitable"
|+ 68000 Instruction Set Table
! rowspan=2|Mnemonic !! colspan="3" | Size !! rowspan=2|Description !! rowspan=2|Operation !! colspan="5" | Condition Codes
|-
! B !! W !! L !! X !! N !! Z !! V !! C
|-
| ABCD || B || || || Add Decimal with Extend || (Destination)⏨ + (Source)⏨ + X → Destination || * || U || * || U || *
|-
| ADD || B || W || L || Add Binary || (Destination) + (Source) → Destination || * || * || * || * || *
|-
| ADDA || || W || L || Add Address || (Destination) + (Source) → Destination || – || – || – || – || –
|-
| ADDI || B || W || L || Add Immediate || (Destination) + Immediate Data → Destination || * || * || * || * || *
|-
| ADDQ || B || W || L || Add Quick || (Destination) + Immediate Data → Destination || * || * || * || * || *
|-
| ADDX || B || W || L || Add Extended || (Destination) + (Source) + X → Destination || * || * || * || * || *
|-
| AND || B || W || L || AND Logical || (Destination) ∧ (Source) → Destination || – || * || * || 0 || 0
|-
| ANDI || B || W || L || AND Immediate || (Destination) ∧ Immediate Data → Destination || – || * || * || 0 || 0
|-
| ANDI to CCR || B || || || AND Immediate to Condition Codes || (Source) ∧ CCR → CCR || * || * || * || * || *
|-
| ANDI to SR || || W || || AND Immediate to Status Register || (Source) ∧ SR → SR || * || * || * || * || *
|-
| ASL, ASR || B || W || L || Arithmetic Shift || (Destination) Shifted by < count > → Destination || * || * || * || * || *
|-
| Bcc || || || || Branch Conditionally || If cc then PC + d → PC || – || – || – || – || –
|-
| BCHG || B || || L || Test a Bit and Change || ~(< bit number >) OF Destination → Z
~(< bit number >) OF Destination → < bit number > OF Destination
|| – || – || * || – || –
|-
| BCLR || B || || L || Test a Bit and Clear || ~(< bit number >) OF Destination → Z
0 → < bit number > OF Destination
|| – || – || * || – || –
|-
| BRA || || || || Branch Always || PC + d → PC || – || – || – || – || –
|-
| BSET || B || || L || Test a Bit and Set || ~(< bit number >) OF Destination → Z
1 → < bit number > OF Destination
|| – || – || * || – || –
|-
| BSR || || || || Branch to Subroutine || PC → (SP); PC + d → PC || – || – || – || – || –
|-
| BTST || B || || L || Test a Bit || ~(< bit number >) OF Destination → Z || – || – || * || – || –
|-
| CHK || || W || || Check Register Against Bounds || If Dn < 0 or Dn > (ea) then TRAP || – || * || U || U || U
|-
| CLR || B || W || L || Clear Operand || 0 → Destination || – || 0 || 1 || 0 || 0
|-
| CMP || B || W || L || Compare || (Destination) - (Source) || – || * || * || * || *
|-
| CMPA || || W || L || Compare Address || (Destination) - (Source) || – || * || * || * || *
|-
| CMPI || B || W || L || Compare Immediate || (Destination) - Immediate Data || – || * || * || * || *
|-
| CMPM || B || W || L || Compare Memory || (Destination) - (Source) || – || * || * || * || *
|-
| DBcc || || W || || Test Condition, Decrement and Branch || If ~cc then Dn - 1 → Dn; if Dn ≠ -1 then PC + d → PC || – || – || – || – || –
|-
| DIVS || || W || || Signed Divide || (Destination) / (Source) → Destination || – || * || * || * || 0
|-
| DIVU || || W || || Unsigned Divide || (Destination) / (Source) → Destination || – || * || * || * || 0
|-
| EOR || B || W || L || Exclusive OR Logical || (Destination) ⊕ (Source) → Destination || – || * || * || 0 || 0
|-
| EORI || B || W || L || Exclusive OR Immediate || (Destination) ⊕ Immediate Data → Destination || – || * || * || 0 || 0
|-
| EORI to CCR || B || || || Exclusive OR Immediate to Condition Codes || (Source) ⊕ CCR → CCR || * || * || * || * || *
|-
| EORI to SR || || W || || Exclusive OR Immediate to Status Register || (Source) ⊕ SR → SR || * || * || * || * || *
|-
| EXG || || || L || Exchange Register || Rx ↔ Ry || – || – || – || – || –
|-
| EXT || || W || L || Sign Extend || (Destination) Sign-Extended → Destination || – || * || * || 0 || 0
|-
| JMP || || || || Jump || Destination → PC || – || – || – || – || –
|-
| JSR || || || || Jump to Subroutine || PC → (SP); Destination → PC || – || – || – || – || –
|-
| LEA || || || L || Load Effective Address || < ea > → An || – || – || – || – || –
|-
| LINK || || || || Link and Allocate || An → (SP); SP → An; SP + Displacement → SP || – || – || – || – || –
|-
| LSL, LSR || B || W || L || Logical Shift || (Destination) Shifted by < count > → Destination || * || * || * || 0 || *
|-
| MOVE || B || W || L || Move Data from Source to Destination || (Source) → Destination || – || * || * || 0 || 0
|-
| MOVE to CCR || || W || || Move to Condition Code || (Source) → CCR || * || * || * || * || *
|-
| MOVE to SR || || W || || Move to Status Register || (Source) → SR || * || * || * || * || *
|-
| MOVE from SR || || W || || Move from the Status Register || SR → Destination || – || – || – || – || –
|-
| MOVE USP || || || L || Move User Stack Pointer || USP → An; An → USP || – || – || – || – || –
|-
| MOVEA || || W || L || Move Address || (Source) → Destination || – || – || – || – || –
|-
| MOVEM || || W || L || Move Multiple Registers || Registers → Destination
(Source) → Registers
|| – || – || – || – || –
|-
| MOVEP || || W || L || Move Peripheral Data || (Source) → Destination || – || – || – || – || –
|-
| MOVEQ || || || L || Move Quick || Immediate Data → Destination || – || * || * || 0 || 0
|-
| MULS || || W || || Signed Multiply || (Destination) × (Source) → Destination || – || * || * || 0 || 0
|-
| MULU || || W || || Unsigned Multiply || (Destination) × (Source) → Destination || – || * || * || 0 || 0
|-
| NBCD || B || || || Negate Decimal with Extend || -((Destination)⏨ - X) → Destination || * || U || * || U || *
|-
| NEG || B || W || L || Negate || 0 - (Destination) → Destination || * || * || * || * || *
|-
| NEGX || B || W || L || Negate with Extend || 0 - (Destination) - X → Destination || * || * || * || * || *
|-
| NOP || || || || No Operation || – || – || – || – || – || –
|-
| NOT || B || W || L || Logical Complement || ~(Destination) → Destination || – || * || * || 0 || 0
|-
| OR || B || W || L || Inclusive OR Logical || (Destination) ∨ (Source) → Destination || – || * || * || 0 || 0
|-
| ORI || B || W || L || Inclusive OR Immediate || (Destination) ∨ Immediate Data → Destination || – || * || * || 0 || 0
|-
| ORI to CCR || B || || || Inclusive OR Immediate to Condition Codes || (Source) ∨ CCR → CCR || * || * || * || * || *
|-
| ORI to SR || || W || || Inclusive OR Immediate to Status Register || (Source) ∨ SR → SR || * || * || * || * || *
|-
| PEA || || || L || Push Effective Address || < ea > → (SP) || – || – || – || – || –
|-
| RESET || || || || Reset External Device || – || – || – || – || – || –
|-
| ROL, ROR || B || W || L || Rotate (Without Extend) || (Destination) Rotated by < count > → Destination || – || * || * || 0 || *
|-
| ROXL, ROXR || B || W || L || Rotate with Extend || (Destination) Rotated by < count > → Destination || * || * || * || 0 || *
|-
| RTE || || || || Return from Exception || (SP) → SR; (SP) → PC || * || * || * || * || *
|-
| RTR || || || || Return and Restore Condition Codes || (SP) → CC; (SP) → PC || * || * || * || * || *
|-
| RTS || || || || Return from Subroutine || (SP) → PC || – || – || – || – || –
|-
| SBCD || B || || || Subtract Decimal with Extend || (Destination)⏨ - (Source)⏨ - X → Destination || * || U || * || U || *
|-
| Scc || B || || || Set According to Condition || If cc then 1’s → Destination else 0’s → Destination || – || – || – || – || –
|-
| STOP || || W || || Load Status Register and Stop || Immediate Data → SR; STOP || * || * || * || * || *
|-
| SUB || B || W || L || Subtract Binary || (Destination) - (Source) → Destination || * || * || * || * || *
|-
| SUBA || || W || L || Subtract Address || (Destination) - (Source) → Destination || – || – || – || – || –
|-
| SUBI || B || W || L || Subtract Immediate || (Destination) - Immediate Data → Destination || * || * || * || * || *
|-
| SUBQ || B || W || L || Subtract Quick || (Destination) - Immediate Data → Destination || * || * || * || * || *
|-
| SUBX || B || W || L || Subtract with Extend || (Destination) - (Source) - X → Destination || * || * || * || * || *
|-
| SWAP || || W || || Swap Register Halves || Register [31:16] ↔ Register [15:0] || – || * || * || 0 || 0
|-
| TAS || B || || || Test and Set an Operand || (Destination) Tested → CC; 1 → [7] OF Destination || – || * || * || 0 || 0
|-
| TRAP || || || || Trap || PC → (SSP); SR → (SSP); (Vector) → PC || – || – || – || – || –
|-
| TRAPV || || || || Trap on Overflow || If V then TRAP || – || – || – || – || –
|-
| TST || B || W || L || Test an Operand || (Destination) Tested → CC || – || * || * || 0 || 0
|-
| UNLK || || || || Unlink || An → SP; (SP) → An || – || – || – || – || –
|}
