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== Register Structure File ==

The 68000’s register file is one of its most celebrated features. It provides{| class="wikitable" style="white-space:nowrap;"* ! Register !! Size !! Description !! Notes|-| D0 - D7 || 32-bit || Data Registers (D0–D7): These are 32 bits wide and are used for general|| General-purpose registers for data manipulation (arithmetic and logical operations. However, when operating on logic). Can be accessed as 8-bit (byte or , `.B`), 16-bit (word data, only the lower 8 `.W`), or 16 bits are affected32-bit (long word, `.L`). Not typically used directly for memory addressing.* |-| A0 - A6 || 32-bit || Address Registers (A0–A7): Also 32 bits wide, these || General-purpose registers are primarily used as pointers or index registers for pointer operations and memory addressing modes. A7 doubles as the stack pointer Can be used for some 16-bit/32-bit arithmetic (SPoperations usually affect the full 32 bits). Word operations typically sign-extend to 32 bits.* Status Register |-| A7 (SRSP/USP/SSP)|| 32-bit || Stack Pointer || Two physically separate registers exist: This 16‑bit register comprises an 8‑bit system byte User Stack Pointer (accessible only in supervisor modeUSP) and an 8‑bit user byte known as the condition code register Supervisor Stack Pointer (CCRSSP).**The CCR contains processor uses the standard flags—zero active one based on the S-bit (ZSupervisor state)in the Status Register. Used implicitly by stack operations (`PEA`, carry `LINK`, `UNLK`, `MOVE to/from -(CAn)/(An)+`), overflow subroutine calls (V`JSR`, `BSR`), negative returns (N`RTS`, `RTR`), and extend exceptions.|-| PC (XProgram Counter)|| 32-bit || Points to the address of the next instruction to be fetched. || Although 32-bit internally, the original 68000 had a 24-bit address bus (16MB addressable space). Later variants (68010+) used more address lines. Modified by branches, jumps, calls, returns, exceptions.|-| SR (Status Register) || 16-bit || Holds processor status (Condition Codes) and system control bits. Divided into User Byte (CCR) and System Byte. <br/> '''User Byte (CCR - Condition Code Register, bits 0-7):''' <br/> *bit 0 - C (Carry) <br/> *The bit 1 - V (Overflow) <br/> * bit 2 - Z (Zero) <br/> * bit 3 least significant bits - N (Negative) <br/> * bit 4 - X (Extend) <br/> '''System Byte (bits 8-15):''' <br/> * bit 10, 9 and 10,8 - I2, I1, I0 (Interrupt Mask) of <br/> * bit 13 - S (Supervisor State) <br/> * bit 15 - T (Trace Mode) <br/> (Other bits reserved/unused in base 68000) || User programs can typically only read/write the Status register’s System CCR (lower byte form the interrupt mask). The interrupt priorities are numbered from 1 to 7, with level 7 having the highest prioritySystem Byte modification requires Supervisor privileges. The level 7 interrupt is nonmaskable and thus cannot be disabledX flag used for multi-precision arithmetic.**Bit 13 of the status register is the S flag, which specifies whether the MC68000 is in supervisor mode or user bit determines User/Supervisor mode(and active A7).**Bit 15 of the status register is the T flag, which specifies whether the MC68000 is in trace modebit enables single-step tracing. After each instruction is executed in the trace mode, a trap is forced so that a debugging program can monitor the results of that instruction’s executionI bits control interrupt priority level.|}