Changes
/* Instruction Cycle */
A full instruction cycle requires anywhere from 4 to 18 states for its completion, depending on the kind of instruction involved.
{| class="wikitable"
|+ T-state Definitions
|-
! T-state !! Description
|-
| T1
| A memory address or I/O device number is placed on the Address Bus (A<sub>15-0</sub>); status information is placed on Data Bus (D<sub>7-0</sub>).
|-
| T2
| The CPU samples the READY and HOLD inputs and checks for halt instruction.
|-
| TW (optional)
| Processor enters wait state if READY is low or if HALT instruction has been executed.
|-
| T3
| An instruction byte (FETCH machine cycle), data byte (MEMORY READ, STACK READ) or interrupt instruction (INTERRUPT machine cycle) is input to the CPU from the Data Bus; or a data byte (MEMORY WRITE, STACK WRITE or OUTPUT machine cycle) is output onto the data bus.
|-
| T4, T5 (optional)
| States T4 and T5 are available if the execution of a particular instruction requires them; if not, the CPU may skip one or both of them. T4 and T5 are only used for internal processor operations.
|}
See this [[Media:Intel 8080 details.pdf|Intel 8080 document]], containing a detailed breakdown of machine cycles and T-states.
