Changes
Z80
,The Z80/Z80A was a very popular microprocessor, used in a wide range of applications, from gaming consoles like the [[ColecoVision]], the [[Sega Master System]] and [[Sega GameGear]] to personal computers like the [[ZX81]], [[ZX Spectrum]] and [[MSX]].
The best-selling devices to feature a Zilog Z80 are the [[Sega MegaDrive]] with 40 million units sold [https://segaretro.org/Sega_Mega_Drive#:~:text=The%20Mega%20Drive%20is%20Sega%27s,and%203%20million%20in%20Brazil. Source], and the TI graphing calculators with 90 million units sold [https://drive.google.com/file/d/1PshC6_lvHiBqry2ASsZ5D0AonmW01nxQ/view Source].
The Z80 microprocessor is an 8-bit [[CPU]] with a 4-bit ALU and a 16-bit address bus capable of direct access to 64KB of memory space. The Z80 is a little-endian CPU, meaning it stores 16-bit values with the least significant byte first, followed by the most significant byte.
The Z80 has about 8500 transistors. To put it into perspective, 64KB of DRAM contains 524288 transistors, as 1 bit of DRAM needs 1 transistor. Fun fact: an Amstrad CPC equipped with a 4MB RAM expansion has 32 million transistors dedicated to RAM while the Z80 CPU still has only 8500 transistors.
* P = parity (only for the parity flag)
* V = overflow (only for the parity flag)
==== Registers ====
| jr cc,e || 001cc000 || 20/28/30/38 ee || 3/2 || 12/7 (4,3,5)/(4,3) || M1, MRe(, INT(5)) || if cc then pc += e || Conditional relative jump <br> cc: 00=NZ, 01=Z, 10=NC, 11=C
|-
| djnz e || 00010000 || 10 ee || 4/3 || 13/8 (5,3,5)/(5,3) || M1, INT(1), MRe(, INT(5)) || b -= 1, if b <> != 0 then pc += e || Decrement, Jump Non-Zero
|-
| ret || 11001001 || C9 || 3 || 10 (4,3,3) || M1, MR, MR || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || pc := (sp), sp += 2 || Return
|-
| ex af,af' || 00001000 || 08 || 1 || 4 (4) || M1 || X || X || X || X || X || X || X || X || af <=> af'
|}
<br>
=== Interrupt Acknowledge ===
{| class="wikitable" style="white-space: nowrap;"
|-
! Type !! Cycles !! M-Cycle Sequence !! Effect !! Description
|-
| Non-Maskable Interrupt || 11 (5, 3, 3) || M1, Int(1), MW (Push PCH), MW (Push PCL) || iff2 := iff1, iff1 := 0, sp -= 2, (sp) := pc, pc := 0066h || Highest priority interrupt. Cannot be disabled by `DI`. Fixed vector address. Saves previous IFF1 state.
|-
| Interrupt in Mode 0 || 13+ (Typically 13 for RST) || M1 (IntAck + 2wait), Int(1), plus cycles for fetched instruction (e.g., MW, MW for RST) || Fetches instruction from Data Bus during acknowledge cycle; Executes fetched instruction (usually `RST nn`) || 8080 compatible mode. Relies on interrupting peripheral to supply an instruction byte (typically `RST`). Cycle count depends on the instruction supplied (13T is for a 1-byte `RST`).
|-
| Interrupt in Mode 1 || 13 (7, 3, 3) || M1 (IntAck + 2wait), Int(1), MW (Push PCH), MW (Push PCL) || iff1 := 0, sp -= 2, (sp) := pc, pc := 0038h || Simple mode, always jumps to fixed address `0038h`. No data needed from peripheral during acknowledge.
|-
| Interrupt in Mode 2 || 19 (7, 3, 3, 3, 3) || M1 (IntAck + 2wait), Int(1), MW (Push PCH), MW (Push PCL), MR (Read Vector Low), MR (Read Vector High) || iff1 := 0, sp -= 2, (sp) := pc, pc := '''('''(I << 8) + V''')''' || Most flexible mode. Forms pointer `(I * 256) + V` where `V` is vector byte from peripheral (LSB ignored). Reads 16-bit target address from pointer address. `I` register must be set up beforehand.
|}
