Changes
/* Oddities */
! ''No arg'' !! A !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! ($nnnn) !! $nn !! $nn,X !! $nn,Y !! ($nn,X) !! ($nn),Y !! rel !! N !! V !! D !! I !! Z !! C
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| ADC BIT || || || 69 (2) || 6D 2C (4) || 7D (4+p) || 79 (4+p) || || 65 24 (3) || 75 (4) || || 61 (6) || 71 (5+p) || || N || V || - || - || Z || C - || A + ∧ M + CF , M<sub>7</sub> → ANF, CF || ADd with Carry|-| SBC || || || E9 (2) || ED (4) || FD (4+p) || F9 (4+p) || || E5 (3) || F5 (4) || || E1 (M<sub>6) || F1 (5+p) || || N || V || - || - || Z || C || A - M - (1 - CF) </sub> → A || SuBtract with Carry|-| CMP || || || C9 (2) || CD (4) || DD (4+p) || D9 (4+p) || || C5 (3) || D5 (4) || || C1 (6) || D1 (5+p) || || N || - || - || - || Z || C || A - M VF || CoMPare accumulatortest BITs
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| AND || || || 29 (2) || 2D (4) || 3D (4+p) || 39 (4+p) || || 25 (3) || 35 (4) || || 21 (6) || 31 (5+p) || || N || - || - || - || Z || - || A ∧ M → A || bitwise AND with accumulator
| ORA || || || 09 (2) || 0D (4) || 1D (4+p) || 19 (4+p) || || 05 (3) || 15 (4) || || 01 (6) || 11 (5+p) || || N || - || - || - || Z || - || A ∨ M → A || bitwise OR with Accumulator
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| BIT ADC || || || 69 (2) || 2C 6D (4) || 7D (4+p) || 79 (4+p) || || 24 65 (3) || 75 (4) || || 61 (6) || 71 (5+p) || || N || V || - || - || Z || - C || A ∧ + M, M<sub>7</sub> + CF → NFA, M<sub>CF || ADd with Carry|-| SBC || || || E9 (2) || ED (4) || FD (4+p) || F9 (4+p) || || E5 (3) || F5 (4) || || E1 (6</sub> ) || F1 (5+p) || || N || V || - || - || Z || C || A - M - (1 - CF) → VF A || SuBtract with Carry|-| CMP || || || C9 (2) || CD (4) || DD (4+p) || D9 (4+p) || || C5 (3) || D5 (4) || || C1 (6) || D1 (5+p) || || N || - || - || - || Z || C || A - M || test BITsCoMPare accumulator
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| CPX || || || E0 (2) || EC (4) || || || || E4 (3) || || || || || || N || - || - || - || Z || C || X - M || ComPare X register
| STY || || || 8C (4) || || || || 84 (3) || 94 (4) || || || || || - || - || - || - || - || - || Y → M || STore Y register
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| PHA TAX || 48 AA (32) || || || || || || || || || || || || - N || - || - || - || - Z || - || A↓ A → X || PusH AccumulatorTransfer A to X
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| PHP TXA || 08 8A (32) || || || || || || || || || || || || - N || - || - || - || - Z || - || P↓ X → A || PusH Processor statusTransfer X to A
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| PLA TAY || 68 A8 (42) || || || || || || || || || || || || N || - || - || - || Z || - || (S)↑ A → A Y || PuLl AccumulatorTransfer A to Y
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| PLP TYA || 28 98 (42) || || || || || || || || || || || || N || V - || D - || I - || Z || C - || (S)↑ Y → P A || PuLl Processor statusTransfer Y to A
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| TAX TSX || AA BA (2) || || || || || || || || || || || || N || - || - || - || Z || - || A S → X || Transfer A Stack pointer to X
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| TAY TXS || A8 9A (2) || || || || || || || || || || || || N - || - || - || - || Z - || - || A X → Y S || Transfer A X to YStack pointer
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| TSX PLP || BA 28 (24) || || || || || || || || || || || || N || - V || - D || - I || Z || - C || (S )↑ → X P || Transfer Stack pointer to XPuLl Processor status
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| TXA PLA || 8A 68 (24) || || || || || || || || || || || || N || - || - || - || Z || - || X (S)↑ → A || Transfer X to APuLl Accumulator
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| TXS PHP || 9A 08 (23) || || || || || || || || || || || || - || - || - || - || - || - || X → S P↓ || Transfer X to Stack pointerPusH Processor status
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| TYA PHA || 98 48 (23) || || || || || || || || || || || || N - || - || - || - || Z - || - || Y → A A↓ || Transfer Y to APusH Accumulator
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| JSR || || || 20 (6) || || || || || || || || || || - || - || - || - || - || - || PC + 2↓, [PC + 1] → PCL, [PC + 2] → PCH || Jump to SubRoutine
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| BRK RTS || 00 60 (76) || || || || || || || || || || || || - || - || - || 1 - || - || - || PC + 2↓, [FFFE] (S)↑ → PCL, [FFFF] (S)↑ → PCH , PC + 1 → PC || BReaKReTurn from Subroutine
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| RTI || 40 (6) || || || || || || || || || || || || N || V || D || I || Z || C || (S)↑ → P, (S)↑ → PCL, (S)↑ → PCH || ReTurn from Interrupt
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| RTS BRK || 60 00 (67) || || || || || || || || || || || || - || - || - || - 1 || - || - || (S)↑ PC + 2↓, [FFFE] → PCL, (S)↑ [FFFF] → PCH, PC + 1 → PC || ReTurn from SubroutineBReaK
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| CLV SEI || B8 78 (2) || || || || || || || || || || || || - || 0 || - || - || - || - || 0 → VF || CLear oVerflow flag|-| CLD || D8 (2) || || || || || || || || || || || || - || - || 0 || - 1 || - || - || 0 1 → DF IF || CLear Decimal SEt Interrupt flag
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| CLI || 58 (2) || || || || || || || || || || || || - || - || - || 0 || - || - || 0 → IF || CLear Interrupt flag
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| SEC || 38 (2) || || || || || || || || || || || || - || - || - || - || - || 1 || 1 → CF || SEt Carry flag
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| CLC || 18 (2) || || || || || || || || || || || || - || - || - || - || - || 0 || 0 → CF || CLear Carry flag
| SED || F8 (2) || || || || || || || || || || || || - || - || 1 || - || - || - || 1 → DF || SEt Decimal flag
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| SEI CLD || 78 D8 (2) || || || || || || || || || || || || - || - || - 0 || 1 - || - || - || 1 0 → IF DF || SEt Interrupt CLear Decimal flag
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| SEC CLV || 38 B8 (2) || || || || || || || || || || || || - || - 0 || - || - || - || 1 - || 1 0 → CF VF || SEt Carry CLear oVerflow flag
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| NOP || EA (2) || || || || || || || || || || || || - || - || - || - || - || - || No operation || No OPeration
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| BCC BPL || || || || || || || || || || || || 90 10 (2+t+p) || - || - || - || - || - || - || Branch on CF NF = 0 || Branch on Carry ClearPLus
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| BCS BMI || || || || || || || || || || || || B0 30 (2+t+p) || - || - || - || - || - || - || Branch on CF NF = 1 || Branch on Carry SetMInus
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| BEQ BVC || || || || || || || || || || || || F0 50 (2+t+p) || - || - || - || - || - || - || Branch on ZF VF = 1 0 || Branch on EQualoVerflow Clear
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| BMI BVS || || || || || || || || || || || || 30 70 (2+t+p) || - || - || - || - || - || - || Branch on NF VF = 1 || Branch on MInusoVerflow Set
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| BNE BCC || || || || || || || || || || || || D0 90 (2+t+p) || - || - || - || - || - || - || Branch on ZF CF = 0 || Branch on Not EqualCarry Clear
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| BPL BCS || || || || || || || || || || || || 10 B0 (2+t+p) || - || - || - || - || - || - || Branch on NF CF = 0 1 || Branch on PLusCarry Set
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| BVC BNE || || || || || || || || || || || || 50 D0 (2+t+p) || - || - || - || - || - || - || Branch on VF ZF = 0 || Branch on oVerflow ClearNot Equal
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| BVS BEQ || || || || || || || || || || || || 70 F0 (2+t+p) || - || - || - || - || - || - || Branch on VF ZF = 1 || Branch on oVerflow SetEQual
|}
! ''No arg'' !! #$nn !! $nnnn !! $nnnn,X !! $nnnn,Y !! $nn !! $nn,X !! $nn,Y !! ($nn,X) !! ($nn),Y !! N !! V !! D !! I !! Z !! C
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| ALR DCP (ASRDCM) || || 4B || CF (26) || DF (7) || DB (7) || C7 (5) || D7 (6) || || C3 (8) || D3 (8) || || 0 N || - || - || - || Z || C || A AND oper, 0 M -> [76543210] 1 -> CF M, A - M || AND DEC oper + LSRCMP oper
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| ANC ISC (ISB, INS) || || || 0B EF (26) || FF (7) || FB (7) || E7 (5) || F7 (6) || || E3 (8) || || F3 (8) || N || - V || - || - || Z || C || A AND oper, bit(7) M + 1 -> M, A - M - CF -> A || AND INC oper + set CF as ASLSBC oper
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| ANC2 RLA || || 2B || 2F (26) || 3F (7) || 3B (7) || 27 (5) || 37 (6) || || 23 (8) || || 33 (8) || N || - || - || - || Z || C || M = CF <- [76543210] <- CF, A AND M -> A || ROL oper+ AND oper|-| RRA || || || 6F (6) || 7F (7) || 7B (7) || 67 (5) || 77 (6) || || 63 (8) || 73 (8) || N || V || - || - || Z || C || M = CF -> [76543210] -> CF, bitA + M + CF -> A, CF || ROR oper + ADC oper|-| SLO (ASO) || || || 0F (6) || 1F (7) || 1B (7) || 07 (5) || 17 (6) || || 03 (8) || 13 (8) || N || - || - || - || Z || C || M = CF <- [76543210] <- 0, A OR M -> A || ASL oper + ORA oper|-| SRE (LSE) || || || 4F (6) || 5F (7) || 5B (7) || 47 (5) || 57 (6) || || 43 (8) || 53 (8) || N || - || - || - || Z || C || M = 0 -> [76543210] -> CF , A EOR M -> A || LSR oper + EOR oper|-| LAX || || || AF (4) || || BF (4+p) || A7 (3) || || B7 (4) || A3 (6) || B3 (5+p) || N || - || - || - || Z || - || M -> A -> X || LDA oper + LDX oper|-| SAX (AXS, AAX) || || || 8F (4) || || || 87 (3) || || 97 (4) || 83 (6) || || - || - || - || - || - || - || A AND X -> M || Stores the bitwise AND of A and X|-| LAS (LAR) || || || || || BB (4+p) || || || || || || N || - || - || - || Z || - || M AND SP -> A, X, SP || LDA/TSX oper |-| TAS (XAS, SHS) || || || || || style="color: #CC0000;"|'''9B''' (5) || || || || || || - || - || - || - || - || - || A AND X -> SP, A AND X AND (H+ set CF as ROL1) -> M || Puts A AND X in SP and stores A AND X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| SHA (AHX, AXA) || || || || || style="color: #CC0000;"|'''9F''' (5) || || || || || style="color: #CC0000;"|'''93''' (6) || - || - || - || - || - || - || A AND X AND (H+1) -> M || Stores A AND X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| SHX (A11, SXA, XAS) || || || || || style="color: #CC0000;"|'''9E''' (5) || || || || || || - || - || - || - || - || - || X AND (H+1) -> M || Stores X AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work|-| SHY (SYA, SAY) || || || || style="color: #CC0000;"|'''9C''' (5) || || || || || || || - || - || - || - || - || - || Y AND (H+1) -> M || Stores Y AND (high-byte of addr + 1) at addrunstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work
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| ANE (XAA) || || style="color: #CC0000;"|'''8B''' (2) || || || || || || || || || N || - || - || - || Z || - || (A OR magic) AND X AND oper -> A || * AND X + AND oper
Turrican 3 on C64 requires a different magic constant than $EE for ANE. $EF is recommended by Groepaz (VICE team)
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| LXA (LAX) || || style="color: #CC0000;"|'''AB''' (2) || || || || || || || || || N || - || - || - || Z || - || (A OR magic) AND oper -> A -> X || Store * AND oper in A and X
highly unstable: involves a 'magic' constant that depends on temperature, the chip series, and maybe other factors.
Wizball on C64 requires a $EE magic constant for LXA
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| ALR (ASR) || || 4B (2) || || || || || || || || || 0 || - || - || - || Z || C || A AND oper, 0 -> [76543210] -> CF || AND oper + LSR
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| ARR || || 6B (2) || || || || || || || || || N || V || - || - || Z || C || A AND oper, CF -> [76543210] -> CF || AND oper + ROR
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| DCP (DCM) ANC || || || CF 0B (62) || DF (7) || DB (7) || C7 (5) || D7 (6) || || C3 (8) || D3 (8) || || N || - || - || - || Z || C || M - 1 A AND oper, bit(7) -> M, A - M CF || DEC AND oper + CMP operset CF as ASL
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| ISC ANC2 || || 2B (ISB, INS2) || || || EF (6) || FF || || || || || N || - || - || - || Z || C || A AND oper, bit(7) -> CF || FB AND oper + set CF as ROL|-| SBX (7AXS, SAX) || E7 || CB (52) || F7 || || || || || || || || N || - || - || - || Z || C || (6A AND X) - oper -> X || CMP and DEX at once, sets flags like CMP|-| E3 USBC (8SBC) || F3 || EB (82) || || || || || || || || || N || V || - || - || Z || C || M + 1 -> M, A - M - ~CF -> A || INC SBC oper + SBC operNOP
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| JAM (KIL, HLT) || 02, 12, 22,
B2, D2, F2 (X)
|| || || || || || || || || || - || - || - || - || - || - || Stop execution || Halt the CPU. The processor will be trapped infinitely in T1 phase with $FF on the data bus. Reset required.
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| NOP (DOP, TOP) || 1A, 3A, 5A,
74, D4, F4 (4)
|| || || || - || - || - || - || - || - || No operation || No Operation
|}
* Conditional jumps are only 8-bit relative. And unconditional jumps are only 16-bit absolute.
* ADC is the only command for addition. To perform an addition without carry, the carry flag must be cleared manually first. Same with SBC for subtract.
* The TXS instruction does not affect any flag, while all other transfer instructions do.* The BIT instruction copies bit 6 of the memory location to VF, regardless of any arithmetic overflow concept.* The CLV (Clear Overflow Flag) instruction exist , but not the SEV (Set Overflow Flag) instruction.
* On NMOS, INC A and DEC A instructions do not exist. They do exist on CMOS.
* The NOP instruction takes 2 full-cycles. This is the minimum amount of cycles an instruction can take. It is necessary because, while the instruction itself does nothing, it still has to increment the 16-bit PC register.
