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CRTC

12,164 bytes removed, 29 May
[[File:CRTC Type 0.jpg|thumb|right|CRTC Type 0 (Hitachi)]]
[[File:CRTC UMC Type 0.png|thumb|right|CRTC Type 0 (UMC)]]
[[File:CRTC Type 1.png|thumb|right|CRTC Type 1]]
[[File:CRTC6845-Type2.jpg|thumb|right|CRTC Type 2]]
It's important to note that the CRTC chip is primarily designed for character-based displays. It explains why, on the Amstrad CPC, the video memory is organized into a grid of characters rather than a purely linear bitmap.
NOTESNOTE: * This document describes the functionality in terms of the CPC with its separate CRTC and Gate-Array. The Plus has both integrated into the same IC, but could be considered to have two functional blocks, one for CRTC and one for Gate-Array. In this document the term 'Gate-Array' is used, but this also applies to the ASIC.* Much information has been drawn from the [https://shaker.logonsystem.eu/ CRTC Compendium] documentation, condensed and rearranged for clarity. For details, timing diagrams, code examples, coding tips, and more, refer to that documentation. <br>
== Overview ==
The 6845 Cathode Ray Tube Controller (CRTC) is a programmable IC used to generate video displays. This IC is used in a variety of computers including the Amstrad CPC, Amstrad Plus CPC+ and KC Compact.
The CRTC is a simple chip. It is made up of counters and equality operators, tied by simple logic. All the complexity stems from its multiple independent implementations with their subtle differences.
This table lists the known ICs used, with their part number, manufacturer and type number.
{| class="wikitable"{{Prettytable|width: 700px; font-size: 2em;}}!|''Part number!''||''Manufacturer!''||''Type number (note 3)''
|-
|HD6845S||Hitachi||0
|AMS40489||Amstrad||3 (note 1)
|-
|AMS4022640226||Amstrad||4 (note 2)
|}
'''NOTES'''
1. The CRTC functionality is integrated into the CPC+ ASIC. This type exists only in the 464 PlusCPC464+, 6128 Plus CPC6128+ and GX4000.
2. This type exists in "cost-down" CPC464 and CPC6128 systems. In the "cost-down" the CRTC functionality is integrated into a single ASIC IC. This ASIC is often refered to as the "Pre-ASIC" because it preceeded the CPC+ ASIC. The CRTC functionality of the Pre-ASIC is almost identical to the CRTC within the ASIC.
3. In the Amstrad community each 6845 implementation has been assigned a type number. This type identifies a group of implementations which operate in exactly the same way. The  As far as I know, the type number system was originally used by demo programmers.
It is possible to detect the 6845 present using software methods, and this is done to:
* warn that the software was not designed for the detected 6845 and may function incorrectly,
* to adapt the software so that it will run with the detected 6845
* In most cases, the type of the detected 6845 is reported.
<br>4. As far as I know, the KC compact used HD6845R only. == Timings and relating with Z80 instructions count == Some informations like : how many Z80 instructions can I fit within a scan line ? Within a screen ? Etc... See http://www.cpcwiki.eu/forum/programming/frame-flyback-and-interrupts/msg25106/#msg25106(To be extracted/edited to conform to wiki good practices).
==Programming==
The CRTC is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. Therefore, executing an IN instruction to the select or write functions causes the CRTC to write the unpredictable data provided by the high-impedance bus to its registers.
<br> === Z80 I/O access timings === The clock provided to the CRTC by the ASIC/Pre-ASIC is phase-shifted compared to the one provided by the Gate Array. {| class="wikitable"|+! Instructions !! Duration !! I/O CRTCs 0/1/2 !! I/O CRTCs 3/4|-| OUT (C),r8 || 4 µsec || '''3rd µsec''' || 4th µsec|-| OUT (C),0 || 4 µsec || '''3rd µsec''' || 4th µsec|-| OUT (n),A || 3 µsec || 3rd µsec || 3rd µsec|-| OUTI || 5 µsec || 5th µsec || 5th µsec|-| OUTD || 5 µsec || 5th µsec || 5th µsec|-| IN r8,(C) || 4 µsec || 4th µsec || 4th µsec|-| INI || 5 µsec || '''4th µsec''' || '''4th µsec'''|-| IND || 5 µsec || '''4th µsec''' || '''4th µsec'''|-| IN A,(n) || 3 µsec || 3rd µsec || 3rd µsec|} <br> ==Video Memory Address (VMA)Addressing==
The VMA of the [[Gate Array]] is constructed from the CRTC MA and RA signals:
==== Interline border ====
On CRTCs 0/2, R1>R0 generates one byte (0.5µs) of border at the end of the raster line. On CRTCs 1/3/4, it does not.
 
If border skew is used, the border byte will skew and change into a full character-width border instead.
 
==== Border conflict ====
If R1=0 and HCC=0, we expect HBORDER to activate as HCC=R1 and we also expect HBORDER to deactivate as HCC=0. In this situation, all CRTCs activate HBORDER.
 
If R6=0 and VCC=0, we expect VBORDER to activate as VCC=R6 and we also expect VBORDER to deactivate as VCC=0. In this situation, all CRTCs activate VBORDER. On CRTC 1, even SBORDER is activated. But on CRTCs 0/2, the first raster line shows an alternation of bytes of VBORDER and displayable characters.
To see the border bytes with your own eyes, type this BASIC line after reset:
</pre>
<br>== HSYNC and VSYNC ==
== On CPC, HSYNC ==and VSYNC from the CRTC are passed into the Gate-Array.
The When HSYNC signal from the CRTC is not directly connected to active Gate-Array outputs the displaypalette colour black. It If the HSYNC is passed set to the [[Gate Array]] 14 characters then black will be output for further modification. See its wiki page14us.
While The HSYNC is active, all modified before being sent to the monitor. It happens 2us after the HSYNC from the CRTC counters continue to increment normally and addresses continue lasts 4us when HSYNC length is greater or equal to be generated6.
On all CRTCsIf R2=46, while an and HSYNC width is ongoing, the condition HCC=R2 is ignored. So we cannot trigger a new HSYNC during an HSYNC14 then monitor hsync starts at 48 and lasts until 51.
=== Contiguous HSYNCs ===On a CPC monitor, the HSYNC is rendered in "absolute black". It is darker than the black output by the Gate-Array.
On CRTC 0, two HSYNCs cannot be contiguousThe VSYNC is also modified before being sent to the monitor. They are always separated by at least 1 CRTC character. What It happens is that when HSC=R3 and HCC=R2, two lines* after the condition HSC=R3 takes precedence over VSYNC from the condition HCC=R2 CRTC and HSYNC stay two lines (same cut rule if VSYNC is stoppedlower than 4). PAL (50Hz) does need two lines VSYNC_width, and 4us HSYNC_width.
On CRTCs 1/2/3/4Using CRTC1, HSYNCs can be contiguousVSYNC width value 0 means a value of 16.
=== Signal delay === On all CRTCs, there is a 1µs delay in display between when the CRTC provides a video pointer, and when the Gate Array displays the corresponding 16-bit character. But on CRTCs 0/1/2, there is no delay for HSYNC. On CRTCs 3/4, the Amstrad engineers fixed the issue by adding a 1µs delay for the HSYNC signal to match the display signal.  So now we have a bigger issue: on CRTCs 3/4, HSYNC occurs 1µs later than on CRTCs 0/1/2. Interrupts being dependent on HSYNC, this is a serious compatibility issue for time-sensitive code. It also explains why the CTM monitor has to be calibrated differently on CRTCs 3/4. Fortunately, the issue is easy to fix, by adjusting the HSYNC width with CRTC register 3. === Discolouration effect === On CRT monitors from other brands, a colour calibration can happen just after the C-HSYNC pulse. So even when a fully valid C-HSYNC pulse of 4µs is emitted, an HSYNC shorter than usual combined with a coloured border can induce a discolouration effect on those monitors. === Screen wobbling and Fine horizontal hardware scroll === These effects use invalid HSYNC signals, which are poorly supported by modern displays. However, these effects were used in commercial-era CPC games, so it's fine if you choose to use them. When R2 increases by 1, the screen is shifted to the left by 16 mode2 pixels. When R2 decreases by 1, the screen is shifted to the right by 16 mode2 pixels. When R3l increases by 1 (and if <6), the screen is shifted to the left by 8 mode2 pixels. When R3l decreases by 1 (and if >2), the screen is shifted to the right by 8 mode2 pixels. The shift is not instantaneous but follows a logarithmic attenuation across several raster lines. This property can be used to get even finer horizontal control by modifying R2/R3 on each raster line. [[Longshot]] has demonstrated [https://youtu.be/1q7RQykZoKY horizontal hardware scroll] with one-pixel precision in mode1 on all CRTCs. However, because you have to synchronize with each line, it takes a lot of CPU time if it's done in fullscreen (272 lines). <br> == VSYNC == The VSYNC signal from the CRTC is not directly connected to the display. It is passed to the [[Gate Array]] for further modification. See its wiki page. While VSYNC is active, all the CRTC counters continue to increment normally and addresses continue to be generated. On all CRTCs, while a VSYNC is ongoing, the condition VCC=R7 is ignored. So we cannot trigger a new VSYNC during a VSYNC.  On CRTCs 0/1/2, the sole condition to trigger a VSYNC is that VCC=R7. While on CRTCs 3/4, it is necessary to have VCC=R7 and HCC=0 and VLC=0 to trigger a VSYNC. === Blocked VSYNC === On CRTC 0, if R7 is modified with the value of VCC when HCC<2, we are in blocked VSYNC. Then, the VSYNC can no longer occur on VCC=R7 until an unblocking condition is produced (VCC or R7 update). Source: §16.4 "Conditions to consider" of the CRTC Compendium === Ghost VSYNC === On CRTC 2, if a VSYNC is triggered during an HSYNC, the CRTC produces a ghost VSYNC. The CRTC then counts the lines as if a VSYNC were taking place by preventing a new VSYNC from occurring, but without the VSYNC pin being enabled. === PPI VSYNC === The VSYNC pin of the CRTC is directly connected to bit0 of port B of the PPI. There is no delay involved. On Amstrad CPC (not Plus!), it is also possible to reverse the direction of PPI port B to output a "fake" VSYNC signal directly from the PPI to the Gate Array. As an exception, the Ghost VSYNC of CRTC 2 overpowers the Fake VSYNC. === Subpixel vertical hardware scroll === By tuning very precisely when the VSYNC signal is sent to the monitor, Longshot has demonstrated [https://youtu.be/bSjRU6Wye00 vertical hardware scroll] with a precision of 1/128th of a pixel. Furthermore, subpixel vertical scrolling consumes very little CPU. === Mid-VSYNC === On all CRTCs, in both interlace modes, a mid-VSYNC is generated when VCC=R7 on the even field. The VSYNC pulse starts in the middle of the raster line, at HCC=R0/2. As an exception, on CRTCs 3/4, if R7=0 then mid-VSYNC will instead occur on the odd field. Source: §19.7 "Mid-VSYNC" of the CRTC Compendium. <br> == Interlace modes == Note: Some details about the CRTC interlace implementations are missing in this article. Consider it as an introduction to the topic. [[File:CRTC Interlace modes.png]] For a CRTC character line with n raster lines, R9 must be set to n-1 on all CRTCs, regardless of the interlace settings. The exception is for CRTCs 0/3/4 in IVM mode, where R9 must be set to n-2. === Interlace sync mode (ISM) === In this mode, the same information is painted in both fields to enhance readability. Reprogramming the CRTC is not necessary. === Interlace sync and video mode (IVM) === In this mode, alternating lines are displayed in the even and odd field to double the resolution. On the even field, the CRTC displays the lines for which VLC is even. On the odd field, the CRTC displays the lines for which VLC is odd. It is necessary to reprogram the CRTC as if we were building a frame of 624 lines. CRTC 2 is the exception: R4, R5, R6, R7 do not need to be reprogrammed as it considers each character line to be a double character line. === Interlace adjustment line === On all CRTCs, in both interlace modes, an additional line (the 625th line) is added automatically by the CRTC at the end of the even field. This line is added after the lines of the vertical adjustment mode. <br> == CRTC registers 6845 Registers ==
The Internal registers of the 6845 are:
{| class="wikitable"{{Prettytable|width: 700px; font-size: 2em;}}|''Register Index''||''Register Name''||''Range''||''CPC Setting''||''Notes''
|-
!rowspan=2|Register Index!rowspan=20|Register Name!colspan=3|Read/Write!rowspan=2Horizontal Total|Range!rowspan=2|CPC Setting!rowspan00000000||63||Width of the screen, in characters. Should always be 63 (64 characters). 1 character =2|Notes= 1µs.
|-
!CRTC 0!CRTCs |1/2!CRTCs 3/4||Horizontal Displayed||00000000||40||Number of characters displayed. Once horizontal character count (HCC) matches this value, DISPTMG is set to 1.
|-
|02||Horizontal Total (-1)||colspan=3 style="text-align: center;"|WriteSync Position||00000000||6346||Width of When to start the screen, in characters. Should always be 63 (64 characters). 1 character == 1μsHSync signal.
|-
|13||Horizontal Displayedand Vertical Sync Widths||colspan=3 style="text-align: center;"VVVVHHHH|Write|128+14|00000000||40||Number of HSync pulse width in characters displayed. Once horizontal character count (HCC0 means 16 on some CRTC) matches this value, DISPTMG is set to 1should always be more than 8; VSync width in scan-lines.(0 means 16 on some CRTC. Not present on all CRTCs, fixed to 16 lines on these)
|-
|24||Horizontal Sync PositionVertical Total||colspan=3 style="text-align: center;"x0000000|Write|38|00000000||46||When to start Height of the HSync signalscreen, in characters.
|-
|35||Horizontal and Vertical Sync WidthsTotal Adjust||colspan=3 style="text-align: center;"xxx00000|Write|0|VVVVHHHH||128+14||VSync width Measured in scan-lines (Not present on all CRTCsscanlines, fixed to 16 lines can be used for smooth vertical scrolling on these) ; HSync pulse width in charactersCPC.
|-
|46||Vertical Total (-1)||colspan=3 style="text-align: center;"|WriteDisplayed||x0000000||3825||Height of the displayed screen, in characters. Once vertical character count (VCC) matches this value, DISPTMG is set to 1.
|-
|57||Vertical Total AdjustSync position||colspan=3 style="text-align: center;"x0000000|Write|30|xxx00000||0||Measured When to start the VSync signal, in scanlines, can be used for smooth vertical scrolling on CPCcharacters.
|-
|68||Vertical DisplayedInterlace and Skew||colspan=3 style="text-align: center;"xxxxxx00|Write|0|x0000000||25||Height of displayed screen in characters. Once vertical character count (VCC) matches this value, DISPTMG is set to 1.00: No interlace; 01: Interlace Sync Raster Scan Mode; 10: No Interlace; 11: Interlace Sync and Video Raster Scan Mode
|-
|79||Vertical Sync PositionMaximum Raster Address||colspan=3 style="text-align: center;"xxx00000|Write|7|x0000000||30||When to start the VSync signalMaximum scan line address on CPC can hold between 0 and 7, in characters.higher values' upper bits are ignored
|-
|810||Interlace and SkewCursor Start Raster||colspan=3 style="text-align: center;"|Write||CCDDxxIIxBP00000||0||CC: Cursor Skew (Only in CRTCs 0, 3 and 4)not used on CPC. DD: Display Skew B = Blink On/Off; P = Blink Period Control (Only in CRTCs 0, 3 and 4Slow/Fast). II: Interlace ModeSets first raster row of character that cursor is on to invert.
|-
|911||Maximum Cursor End Raster Address (aka Number of Scan Lines) (-1)||colspan=3 style="text-align: center;"|Write||xxx00000||70||Maximum scan line address Sets last raster row of character that cursor is on CPC can hold between 0 and 7, higher values' upper bits are ignored.to invert
|-
|1012||Cursor Display Start RasterAddress (High)||style="text-align: center;"xx000000|Write||style="text-align: center;"|Write||Read/Write||xBP00000||0||B = Blink On/Off; P = Blink Period Control (16 or 32 frames). Sets first raster row of character that cursor is on to invert.48
|-
|1113||Cursor End RasterDisplay Start Address (Low)||style="text-align: center;"|Write||style="text-align: center;"|Write||Read/Write||xxx0000000000000||0||Sets last raster row Allows you to offset the start of character that cursor is on to invertscreen memory for hardware scrolling, and if using memory from address &0000 with the firmware.
|-
|1214||Display Start Cursor Address (High)||Read/Write||style="text-align: center;"|Write||Read/Write||xx000000||48||On Amstrad Plus, bit7 of the printer port is controlled by bit3 of CRTC R12 (ie. bit11 of Display Start Address).0
|-
|1315||Display Start Cursor Address (Low)||Read/Write||style="text-align: center;"|Write||Read/Write||00000000||0||Allows you to offset the start of screen memory for hardware scrolling, and if using memory from address &0000 with the firmware.
|-
|1416||Cursor Light Pen Address (High)||colspan=3 style="text-align: center;"|Read/Write||xx000000||0||Read Only
|-
|15||Cursor Address (Low)||colspan=3 style="text-align: center;"|Read/Write||00000000||0|||-|16||Light Pen Address (High)||colspan=3 style="text-align: center;"|Read||xx000000||||On CRTC1, bit6 of Status register goes to 0 when R16 is read.|-|17||Light Pen Address (Low)||colspan=3 style="text-align: center;"|Read||00000000||||On CRTC1, bit6 of Status register goes to 0 when R17 is read.Read Only
|-
|}
 
registers 18-31 read as 0, on type 0 and 2.
registers 18-30 read as 0 on type1, register 31 reads as 0x0ff.
<br>
<br>
=== Register access =CRTC Differences ==
On CRTCs 0/1/2, if a Write Only register is read from, "0" is returned. The register accessing scheme on CRTCs 3/4 makes it impossible In this section I will attempt to happenidentify all the differences between each CRTC.
On all CRTCs, only The following tables list the 5 least significant bits of the selected register number are considered to write to a register. The other bits are ignored.functions that can be accessed for each type:
On CRTCs Type 0/1/2, only the 5 least significant bits of the selected register number are considered to read a register:* On CRTCs 0/2, registers 18-31 read as 0* On CRTC 1, registers 18-30 read as 0, register 31 reads as &FF
On CRTCs 3/4, only the 3 least significant bits of the selected register number are considered to read a register, according to the following table: {| class="wikitable"{{Prettytable|width: 700px; font-size: 2em;}}!Nb!Register!Definition|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||R160||Light Pen Address (High)Select internal 6845 register||Write Only
|-
|0||1||R17Write to selected internal 6845 register||Light Pen Address (Low)Write Only
|-
|21||R100||Cursor Start Raster-||-
|-
|31||R111||Cursor End RasterRead from selected internal 6845 register||Read only
|-
|4} Type 1 {|{{Prettytable|R12width: 700px; font-size: 2em;}}|''b1''|Display Start Address (High)|''b0''||''Function''||''Read/Write'' |-|0||0||Select internal 6845 register||Write Only
|-
|50||R131||Display Start Address (Low)Write to selected internal 6845 register||Write Only
|-
|61||R140||Cursor Address (High)Read Status Register||Read Only
|-
|71||R151||Cursor Address (Low)Read from selected internal 6845 register||Read only
|}
<br>Type 2
== CRTC {|{{Prettytable|width: 700px; font-size: 2em;}}|''b1''||''b0''||''Function''||''Read/Write'' |-|0||0||Select internal 6845 register differences ==||Write Only |-|0||1||Write to selected internal 6845 register||Write Only |-|1||0||-||- |-|1||1||Read from selected internal 6845 register||Read only |-|}
CRTC types Type 3 and 4 are identical in every way, except for the unlocking mechanism, split screen, hardware soft scroll and 8-bit printer port functionalities specific to the [[ASIC]].
<br>{|{{Prettytable|width: 700px; font-size: 2em;}}|''b1''||''b0''||''Function''||''Read/Write'' |-|0||0||Select internal 6845 register||Write Only |-|0||1||Write to selected internal 6845 register||Write Only |-|1||0||Read from selected internal 6845 register||Read Only |-|1||1||Read from selected internal 6845 register||Read only |-|}
=== R10It is not possible to read from all the internal registers, this table shows the read/R11 on ASIC/Pre-ASIC ===write status of each register for each type:
The cursor raster registers R10/R11 act as status registers when read on CRTCs 3/4. They behave as normal cursor raster registers upon write. {| class="wikitable"! R10 {{Prettytable|width: 700px; font- Bit numbersize: 2em;}}! Bit value! Event|rowspan=2|''Register Index''||rowspan=2|''Register Name''||colspan=4|''Type''
|-
|0||1|C0=R0|2||3||4
|-
|1|0|C0=R0/|Horizontal Total||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|1||Horizontal Displayed||Write Only||Write Only||Write Only||(note 2)|0|C0=R1-1 (if R0>=R1note 3)
|-
|32|0|C0=R2Horizontal Sync Position||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|43|0|C0=R2+R3Horizontal and Vertical Sync Widths||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|54||Vertical Total||Write Only||Write Only||Write Only|01|R3h>0 : C0=0..R0 on the line R3h from Vsync (C4=R7note 2)R3h=0 : C0=0..R0 over 15 lines from Vsync ||(C4=R7note 3)
|-
|65|1|Always 1Vertical Total Adjust||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|76||Vertical Displayed||Write Only||Write Only||Write Only|00|C0=0..R0-1 : VMA.Lsb=0xFFC0=R0 : VMA'.Lsb=0x00 (same cond if C0=R0=0note 2)|} {| class="wikitable"! R11 - Bit number! Bit value! Event(note 3)
|-
|07|0|C4=R4 and C9=R9 and C0=R0 : Last char of screenVertical Sync position||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|18|0|C4=R6-1 Interlace and C9=R9 and C0=R0 : Last char displayedSkew||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|9||Maximum Raster Address||Write Only||Write Only||Write Only||(note 2)|0|C4=R7-1 and C9=R9 and C0=R0 : Last char before Vsync(note 3)
|-
|310|0/1|Timer 16 CRTC framesCursor Start Raster||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|411|1|Always 1Cursor End Raster||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|512|0|C9=R9 : C0=0 to R0Display Start Address (High)||Read/Write||Write Only||Write Only||Read/Write (note 2)||(note 3)
|-
|613||Display Start Address (Low)||Read/Write||Write Only||Write Only||Read/Write (note 2)||(note 3) |0-|Always 014||Cursor Address (High)||Read/Write||Read/Write||Read/Write||Read/Write (note 2)||(note 3)|-|15||Cursor Address (Low)||Read/Write||Read/Write||Read/Write||Read/Write (note 2)||(note 3)|-|16||Light Pen Address (High)||Read Only||Read Only||Read Only||Read Only (note 2)||(note 3)|-|17||Light Pen Address (Low)||Read Only||Read Only||Read Only||Read Only (note 2)||(note 3)
|-
|7
|1
|(C9=R9 and C0=R0) or (C9=0 and C0=0 to R0-1)
|}
<br>'''Notes''' 1. On type 0 and 1, if a Write Only register is read from, "0" is returned.  2. See the document "Extra CPC Plus Hardware Information" for more details. 3. CRTC type 4 is the same as CRTC type 3. The registers also repeat as they do on the type 3. == Horizontal and Vertical Sync (R3) ==
=== Horizontal and Vertical Sync (R3) ===
<br>
==UM6845R and R12/R13 = Status register on Type = The UM6845R differs to other CRTC in respect of R12/R13.  When VCC=0, R12/R13 is re-read at the start of each line. R12/R13 can therefore be changed for each scanline when VCC=0.  Just like other CRTCs when RC==(R9-1 ), the current MA is captured for the next char-line. In demos to make a display compatible with all CRTCs program R12/R13 when VCC!=0. This will then take effect at the next frame start. == UM6845R status register ==
The UM6845R has a status register that can be read using port &BExx.
Bit 6 is set to 1 if there is a strobe input to the /LPEN signal. It is cleared to 0 when either R17 or R16 (LPEN address) of the CRTC are read. It signals there is a valid LPEN input. On Kevin Thacker's my CPC (arnoldemu) with UM6845R, it is triggered at power on, R17 and R16 have the values 0 when read.
Bit 5 is set to 1 when CRTC is in "vertical blanking". Vertical blanking is when the vertical border is active. i.e. VCC>=R6.
All the other bits read as 0 and don't have any function.
<br>== CRTC Type Detection ==
== It is possible to detect the CRTC Type using software methods, and this is done to:  * warn that the software was not designed for the detected 6845 and may function incorrectly* to adapt the software so that it will run with the detected 6845 * In most cases, the type of the detected 6845 is reported Detection ==routine in BASIC:
<pre>
10 MODE 1:' Reinitialize screen
[[File:CRTC timing small.gif]]
 
<br>
 
== Internal Counters ==
 
{| class="wikitable"
! Counter name
! Abbr
! Alternate name
! Compared with
! Comment
|-
|Horizontal Character Counter
|HCC
|C0
|R0, R1, R2
| Increments on every clock cycle
|-
|Horizontal Sync Counter
|HSC
|C3l
|R3l
|
|-
|Vertical Character Counter
|VCC
|C4
|R4, R6, R7
|
|-
|Vertical Sync Counter
|VSC
|C3h
|R3h
|R3h is fixed to 0 on CRTCs 1/2. This gives 16 lines of VSYNC
|-
|Vertical Line Counter
|VLC
|C9
|R9, R10, R11
|If not in IVM mode, this counter is exposed on CRTC pins RA0..RA4
|-
|Vertical Total Adjust Counter
|VTAC
|C5
|R5
|This counter does not exist on CRTCs 0/3/4. C9 is reused instead
|-
|Frame Counter
|FC
|
|
|Used to alternate frames in interlace and for CRTC cursor blinking
|-
|Memory Address
|MA
|
|R14/R15
|This counter is exposed on CRTC pins MA0..MA13
|}
 
When IVM mode is activated, VLC continues to increment normally. However, RA is not identical to VLC anymore. Instead, VLC is considered shifted left by 1 bit, and bit0 represents the parity of the field (even/odd).
 
<br>
 
== CRTC counter differences ==
 
=== MA buffering ===
 
No matter its type, the CRTC never buffers any of its counters, except for the video pointer MA. The buffer MA' is needed because MA has to be reloaded at the beginning of every raster line.
 
At the end of the display of the last raster line of each character line (ie. when HCC=R1 and VLC=R9), MA' captures the current value of MA.
 
CRTC 2 is the exception: at the end of the display of the last raster line of the frame, MA' captures R12/R13 instead of MA.
 
<br>
 
=== MA reload ===
 
On CRTCs 0/3/4, at the beginning of the first raster line of the frame, MA and MA' are loaded with R12/R13. Otherwise, MA is loaded with MA'.
 
On CRTC 2, at the beginning of every raster line of the frame (including the first one), MA is loaded with MA'.
 
On CRTC 1, at the beginning of every raster line of the first character line of the frame (ie. when VCC=0), MA is loaded with R12/R13 instead of MA'. '''This is a major source of incompatibility if the programmer does not take care.''' In demos and games, to be compatible with all CRTCs, program R12/R13 only when VCC≠0. This will then take effect at the next CRTC frame start.
 
==== Rupture For Dummies (R5 bug) ====
 
CRTC 1 has a bug that occurs when R5 is updated with a non-zero value when HCC=R0 and VLC≠R9, but only when R5 was previously 0. This changes the MA update source to R12/R13 instead of MA'. The CRTC then loads R12/R13 into MA at the beginning of every scanline, regardless of the VCC value.
 
This R5 bug also messes with the frame parity management. However, it is possible to fix the parity of the frame by activating/deactivating the IVM interlace mode.
 
The vertical adjustment operates normally after the RFD is triggered. If vertical adjustment is not needed, R5 can be reset at any time after the RFD is activated.
 
This CRTC bug divides the CPC demoscene community, with some considering it fully understood, while others find it still perplexing as it seems like the bug itself is bugged.
 
This effect is used in the [https://www.cpc-power.com/index.php?page=detail&num=19308 DSC4 demo].
 
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=== VSC (C3h) overflow ===
 
During a VSYNC on CRTCs 0/3/4, if VSYNC Width (R3h) is changed with a value less than the current VSC, then VSC overflows and will count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3h.
 
On CRTCs 1/2, the VSYNC width is fixed to 16 characters. It is not possible to modify it. Therefore, VSC cannot be overflowed.
 
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=== HSC (C3l) overflow ===
 
During an HSYNC, if HSYNC Width (R3l) is changed with a value less than the current HSC, then HSC overflows and will count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3l.
 
The only exception is for CRTC 1 with a value of 0, which immediately cancels the current HSYNC.
 
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=== VCC (C4) overflow ===
 
On all CRTCs, if Vertical Total (R4) is changed with a value less than VCC, then:
* if this update was done when VCC < R4, then VCC overflows and will count up to its maximum value (127) before looping back and counting up again until it reaches the new value of R4
* if this update was done when VCC = R4, the current character line was already decided to be the last one of the current frame. No update to R4 will make the CRTC change its mind for the current frame
 
The only exception when VCC = R4 is for CRTC 1 with a value of 0, which will cause VCC to overflow.
 
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=== HCC (C0) overflow ===
 
If Horizontal Total (R0) is changed with a value less than the current HCC, then:
* on CRTCs 0/1/2, HCC overflows and will count up to its maximum value (255) before looping back and counting up again until it reaches the new value of R0
* on CRTCs 3/4, the current line is considered finished and HCC is immediately reset to 0 on the next line
 
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=== VLC (C9) overflow ===
 
If Number of Scan Lines (R9) is changed with a value less than the current VLC, then:
* on CRTCs 0/1/2, VLC overflows and will count up to its maximum value (31) before looping back and counting up again until it reaches the new value of R9
* on CRTCs 3/4, the current line is considered the last one of this CRTC character and VLC will reset to 0 on the next line
 
As an exception, on CRTCs 0/2, if VLC is modified during the last frame line, then the updated value will not be considered for the current frame.
 
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=== VTAC (C5/C9) overflow ===
 
During vertical adjustment mode, if Vertical Total Adjust (R5) is changed with a value less than the current VTAC, then:
* on CRTCs 0/1/2, VTAC overflows and will count up to its maximum value (31) before looping back and counting up again until it reaches the new value of R5
* on CRTCs 3/4, the current line is considered the last one of the current frame and vertical adjustment will end
 
As an exception, on CRTCs 0/2, if VTAC is modified during the last frame line, then the updated value will not be considered for the current frame.
 
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=== Vertical Adjustment mode ===
 
On CRTCs 3/4, this mode does not increment VCC, so VCC remains equal to R4.
 
On CRTC 0, this mode increments VCC, causing it to exceed R4, but this increment occurs only once.
 
On CRTCs 1/2, this mode increments VCC, causing it to exceed R4, and this increment can happen multiple times depending on the values of R5 and R9.
 
Also, only CRTCs 1/2 have a dedicated C5 counter. On CRTCs 0/3/4, during Vertical Adjustment, C9 has to fullfil the VTAC role which means that it cannot fullfil its VLC role. This impacts address generation as R9 is not considered anymore.
 
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=== Counter freezes ===
 
On CRTCs 1/2/3/4, R0 accepts all values without causing any problems for counters.
 
On CRTC 0:
* Setting R0 to 0 will cause numerous issues that stem from the fact that VLC is frozen. As HCC never reaches 1, the logic that increments VLC is never triggered.
* The logic that triggers vertical adjustment is broken if R0<2.
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== Datasheets ==
 
==== Used by Amstrad ====
* [[Media:hd6845.hitachi.pdf|HD6845S (Hitachi)]] aka Type 0
* [http://en.wikipedia.org/wiki/6845 Wikipedia on the CRTC]
* [[Media:ACCC1.8-EN.pdf]] CPC CRTC Compendium - Latest (04/2024!) document containing in-depth info about CRTC programming on CPC.
* [[Media:CRTC Compendium Podcast.mp3]] The CRTC Compendium digested in podcast format
* [http://www.grimware.org/doku.php/documentations/devices/crtc CRTC documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:crtc Quasar CRTC documentation (in french)]
* [[Media:Dossier CRTC(Ramlaid Mortel).pdf]] Les entrailles du CRTC
* [https://thecheshirec.at/tag/crtc6845/ Leçons CRTC (CheshireCat)]
* [[Media:ACCC1.8-EN.pdf]] [[Media:ACCC1.8-FR.pdf]] CPC CRTC Compendium - Latest (04/2024!) document containing in-depth info about CRTC programming on CPC.
* [[Media:CRTC Compendium Podcast.mp3]] The CRTC Compendium digested in podcast format
* [https://martin.hinner.info/vga/pal.html PAL video timing specification]
 
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==Related pages==
Longshot
463
edits
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