=== Gate Array Register 3 ===
In the CPC register 3 was not handled by Controls RAM Banking, similar to the Gate-Array. The on CPC6128 (or, more specific, like the 16L8 PAL IC was also mapped at which assists the same I/O address as the Gate-Array and bit 7 and 6 of the data had to be 1 to avoid conflict with other CPC6128s Gate-Array registers).
In the Aleste register 3 is effectively Mapper select.
