Changes
/* RET cc and WAIT_n timing analysis */
In r005.6, cpctest.dsk did pass. Removing MEM_wr:slow both tests does still run fine (NOP/HALT (x00 x76)). Removing full mod4 WAIT_n generator, cpctest.dsk and plustest.dsk does fail. So NOP has to be synchronized ? (plustest.dsk is full of NOPs)
My WAIT_n generator currently passing fully plustest.dsk's testbench is using the bad edge, something is wrong, it's a false positive. I know that NOP, HALT and IO_ACK/INT has to be good for this test to be valid. It's not the case here, so in fact my table of latencies is not the good one : running, but corrections are done on several bad instructions, some of them are even illogical, as finally this "RET cc" instruction where I have had to hack the Z80 itself to reach a passing test, so something is wrong, and that things thing is firstly the current WAIT_n generator clock edge (in comparison againts Z80's clock edge)
Have to change my approach, perhaps using invariant (table of full instruction chrono versus reality), validate instruction timing before trying validating IO_ACK interrupts. Write one table from plustest.dsk's testbench launched on WinAPE, and table from original Z80 documentation, and deduce the table of latencies. I have to trust first in my instruction timing tables (and have to write them both completely...)
