Changes
/* RET cc and WAIT_n timing analysis */
Have to change my approach, perhaps using invariant (table of full instruction chrono versus reality), validate instruction timing before trying validating IO_ACK interrupts. Write one table from plustest.dsk's testbench launched on WinAPE, and another table from original Z80 documentation, and deduce a first theorical candidate table of latencies. I have to trust first in my instruction timing tables (and have to write them both completely...)
Prefixed instruction seems having only one M1 : Z80 doc show that a prefixed instruction take 4T more time. But last time plustest.dsk did pass thinking prefixed instruction are totally separated (M1 for DD, M1 for CB, M1 for "RLC (IX+D)"), so each prefix has its own M1, and following instruction has also its own M1.
Is IO_ACK itself a separated instruction ? I think not, it's more about a hack of a current instruction, adding two autowait and making its business during this inserted times.
