* [[Z80 - undocumented opcodes]]
* [[Media:Z80 CPC Timings cheat sheet.20230709.pdf]]
== Tutorials Block Diagram ==[[File:Z80 Block Diagram.gif]]
== Manuals == *[[Media:Um0080.pdf]] |Official Zilog Z80 CPU user manual from (2016)]]*[http[Media://www.bitsavers.org/components/zilog/z80/03-0029-01_Z80_CPU_Technical_Manual_1977.pdf Official Zilog Z80 CPU technical manual from Technical Manual 1977.pdf]]*[https[Media://deramp.com/downloads/mostek/AID-80F/manuals/MK78515%20Z80%20Programming%20Manual.pdf Mostek Z80 programming manualProgramming Manual.pdf]]
== Weblinks ==
*[http://www.z80.info/z80cs.htm Computer Systems based on Z80 Family]
*[http://en.wikipedia.org/wiki/Z80 The Z80 processor on Wikipedia]
*[https://www.grimware.org/doku.php/documentations/devices/z80 Z80 documentation from Grimware]
== Opcodes ==
Check the end of the document for explanations of abbreviations used below.
=== Alfabethical Alphabetical list ===
{|{{Prettytable|width: 700px; font-size: 2em;}}
|ADD IY, BC||15||2||rowspan=4|--?- 0 *||FD 09||rowspan=4|Add (IY register)||rowspan=4|IY = IY + rr
|-
|ADD IY, DE||15||2||FD 19
|-
|ADD IY, IY||15||2||FD 29
|DAA||4||1||***P-*||27||Decimal Adjust Acc.||A=BCD format (dec.)
|- style="background:#efefef;"
|DEC A||4||1||rowspan=10|***V1-||3D||rowspan=10|Decrement (8-bit)||rowspan=107|s=s-1
|-
|DEC B||4||1||05
|DEC L||4||2||2D
|-
|DEC (HL)||11||1||35||(HL)=(HL)-1
|-
|DEC (IX+N)||23||3||DD 35 XX||rowspan=2|(xx-d)=(xx-d)+1
|-
|DEC (IY+N)||23||3||FD 35 XX
|IN L,(C)||12||2||ED 68
|- style="background:#efefef;"
|INC A||4||1||rowspan=710|***V0-||3C||rowspan=710|Increment (8-bit)||rowspan=7|r=r+1
|- style="background:#efefef;"
|INC B||4||1||04
|- style="background:#efefef;"
|INC L||4||1||2C
|-
|INC (HL)||11||1||34||(HL)=(HL)+1
|- style="background:#efefef;"
|INC (IX+N)||23||3||DD 34 XX||rowspan=2|(xx+d)=(xx+d)+1
|- style="background:#efefef;"
|INC (IY+N)||23||3||FD 34 XX
|-
|INC BC||6||1||rowspan=4|------||03||rowspan=4|Increment (16-bit)||rowspan=4|ss=ss+1
|- style="background:#efefef;"
|INC IY||10||2||FD 23
|-
|INC (HL)||11||1||***V0-||34||Increment (indirect)||(HL)=(HL)+1
|- style="background:#efefef;"
|INC (IX+N)||23||3||rowspan=2|***V0-||DD 34 XX||rowspan=2|Increment||rowspan=2|(xx+d)=(xx+d)+1
|- style="background:#efefef;"
|INC (IY+N)||23||3||FD 34 XX
|-
|IND||16||2||?*??1-||ED AA||Input and Decrement||(HL)=(C),HL=HL-1,B=B-1
|}
=== Sorted by opcode CPC Timings ===
{| class=== Ordered by function ==="wikitable sortable"!Instruction!µs!Size!I/O|-|ADC/ADD/SBC/SUB A, (HL)|2|1||-|ADC/ADD/SBC/SUB A, (IX/IY+d)|5|3||-|ADC/ADD/SBC/SUB A, A/B/C/D/E/H/L|1|1||-|ADC/ADD/SBC/SUB A, HX/LX/HY/LY|2|2||-|ADC/ADD/SBC/SUB A, d|2|2||-|ADD/SUB HL, BC/DE/HL/SP|3|1||-|ADD/SUB IX/IY, BC/DE/HL/SP|4|2||-|AND/OR/XOR A, (HL)|2|1||-|AND/OR/XOR A, (IX/IY+d)|5|3||-|AND/OR/XOR A, A/B/C/D/E/H/L|1|1||-|AND/OR/XOR A, HX/LX/HY/LY|2|2||-|AND/OR/XOR A, d|2|2||-|BIT x, (HL)|3|2||-|BIT x, (IX/IY+d)|6|4||-|BIT x, A/B/C/D/E/H/L|2|2||-|CALL cond, aa|5/3|3||-|CALL aa|5|3||-|CCF/SCF|1|1||-|CP A, (HL)|2|1||-|CP A, (IX/IY+d)|5|3||-|CP A, A/B/C/D/E/H/L|1|1||-|CP A, HX/LX/HY/LY|2|2||-|CP A, d|2|2||-|CPD/CPI|4|2||-|CPDR/CPIR|6/4|2||-|CPL|1|1||-|DAA|1|1||-|DEC/INC (HL)|3|1||-|DEC/INC (IX/IY+d)|6|3||-|DEC/INC A/B/C/D/E/H/L|1|1||-|DEC/INC HX/LX/HY/LY|2|2||-|DEC/INC BC/DE/HL/SP|2|1||-|DEC/INC IX/IY|3|2||-|DI/EI|1|1||-|DJNZ|4/3|2||-|EX (SP), HL|6|1||-|EX (SP), IX/IY|7|2||-|EX AF, AF’|1|1||-|EX DE, HL|1|1||-|EXX|1|1||-|HALT|1|1||-|IM m|2|2||-|IN A/B/C/D/E/H/L, (C)|4|2||-|IN A, (d)|3|2||-|IN F|4|2||-|IND/INI|5|2||-|INDR/INIR|6/5|2||-|JP aa|3|3||-|JP cond, aa|3|3||-|JP (HL)|1|1||-|JP (IX/IY)|2|2||-|JR a|3|2||-|JR cond, a|3/2|2||-|LD (BC/DE), A|2|1||-|LD (HL), A/B/C/D/E/H/L|2|1||-|LD (HL),d|3|2||-|LD (IX/IY+d), A/B/C/D/E/H/L|5|3||-|LD (IX/IY+d), d’|6|4||-|LD (aa), A|4|3||-|LD (aa), BC/DE/SP/IX/IY|6|4||-|LD (aa), HL|5|3||-|LD A, (BC/DE)|2|1||-|LD A/B/C/D/E/H/L, (HL)|2|1||-|LD A/B/C/D/E/H/L, (IX/IY+d)|5|3||-|LD A,(aa)|4|3||-|LD A/B/C/D/E/H/L, A/B/C/D/E/H/L|1|1||-|LD A/B/C/D/E/H/L, d|2|2||-|LD HX/LX, A/B/C/D/E/HX/LX|2|3||-|LD HY/LY, A/B/C/D/E/HY/LY|2|3||-|LD BC/DE/HL/SP, dd|3|3||-|LD IX/IY, dd|4|4||-|LD SP, IX/IY|3|2||-|LD SP, HL|2|1||-| LD HX/LX/HY/LY, d|3|3||-|LD BC/DE/HL/SP/IX/IY, (aa)|6|4||-|LD HL, (aa)|5|3||-|LD A, I/R|3|2||-|LD I/R, A|3|2||-|LDD/LDI|5|2||-|LDDR/LDIR|6/5|2||-|NEG|2|2||-|NOP|1|1||-|OUT (C), A/B/C/D/E/H/L|4|2|3|-|OUT (C), 0|4|2|3|-|OUT (d), A|3|2|3|-|OUTD/OUTI|5|2|5*|-|OTDR/OTIR|6/5|2|5*|-|POP AF/BC/DE/HL|3|1||-|POP IX/IY|4|2||-|PUSH AF/BC/DE/HL|4|1||-|PUSH IX/IY|5|2||-|RES/SET x, (HL)|4|2||-|RES/SET x, (IX/IY+d)|7|4||-|RES/SET x, (IX/IY+d), A/B/C/D/E/H/L|7|4||-|RES/SET x, A/B/C/D/E/H/L|2|2||-|RET|3|1||-|RET cond|4/2|1||-|RETI/RETN|4|2||-|RL/RLC/RR/RRC/SLA/SLL/SRA/SRL (HL)|4|2||-|RL/RLC/RR/RRC/SLA/SLL/SRA/SRL (IX/IY+d)|7|4||-|RL/RLC/RR/RRC/SLA/SLL/SRA/SRL (IX/IY+d), A/B/C/D/E/H/L|7|4||-|RL/RLC/RR/RRC/SLA/SLL/SRA/SRL A/B/C/D/E/H/L|2|2||-|RLA/RLCA/RRA/RRCA|1|1||-|RLD/RRD|5|2||-|RST 0/8/10h/18h/20h/28h/30h/38h|4|1||}
Notes:
*x=[0..7], d=[0..ff], m=[0..2], aa=[0..ffff], a=[0..ff]
* * Some exceptions exist
* All instructions containing (IX/IY+d) add 3µs and 2 bytes compared to their (HL) variants
* Contrarily to what the syntax of the instructions JP (HL/IX/IY) suggest, PC will be loaded with the contents of the register itself, not the indexed value. Those instructions should be understood as JP HL/IX/IY
[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:CPC Internal Components]]