== 8255 Part numbers used in the CPC during its lifetime ==
* Mitsubishi M5L8255AP-5 [https://www.cpcwiki.eu/imgs/8/80/MC0001A-v2-components.jpg Source]* NEC D8255AC-2[https://www.cpcwiki.eu/imgs/d/da/Amstrad_CPC464_Z70200_MC0003A_PCB_Top.jpg Source]* NEC D8255AC-5[https://www.cpcwiki.eu/imgs/c/c6/CPC464_270100_MC0001A_PCB_Top.jpg Source]* Toshiba TMP8255AP-5[https://www.cpcwiki.eu/imgs/0/0d/CPC464_Z70100_MC0001A_PCB_Top.jpg Source]
All of these are almost identical in their operation. It According to Kevin Thacker, it is possible to detect each version by writing and then reading from the ppi control i/o port. Each can give a different pattern of values that are read back. The KP580BB55A is a Soviet clone of the Intel i8255. It is used in the [[KC Compact]] and the [[Aleste 520EX]] clones of the Amstrad CPC computer.
<br>
The [[8255 PPI chip]] is a general purpose input/output IC. This document will describe its role in the Amstrad CPC, CPC+ and KC compact systems. To understand its full functions please read the datasheet.
In these systems it is connected to the [[PSG|AY-3-8912 Programmable Sound Generator (PSG)]], keyboard, cassette recorder, the VSYNC of the [[CRTC|6845 CRTC ]] and the "busy" signal from the parallel port.
The PPI is selected when A11 of the I/O port address is set to "0", A9 and A8 then define the PPI function access (as shown below), A15-A12 and A10 should be "1" (to prevent conflicts with other hardware), A7-A0 are don't care. So, resulting Port addresses are:
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|''!I/O address''||''!/CS (A11)!A1 (A9''||'')!A0 (A8''||'')!Description''||''!Read/Write status''||''!Used Direction''||''!Used for''
|-
|&F4xx||0||0||0||Port A Data||Read/Write||In/Out||[[PSG]] (Sound/Keyboard/Joystick)
|-
|&F5xx||0||0||1||Port B Data||Read/Write||In||Vsync/Jumpers/PrinterBusy/CasIn/Exp
|-
|&F6xx||0||1||0||Port C Data||Read/Write||Out||KeybRow/CasOut/PSG
|-
|&F7xx||0||1||1||Control||Write Only||Out||Control
|-
|}
* for reading data from PSG all bits must be set to input (thereafter, output direction should be restored, for compatibility with the BIOS).
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|''!Bit''||''!Description''||''!Usage''
|-
|7-0||PSG.DATA||[[PSG]] Databus (Sound/Keyboard/Joystick)
* Input
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|''!Bit''||''!Description''||''!Usage in CPC''||''!Usage in [[KC Compact'']]
|-
|7||CAS.IN||Cassette data input||Same as on CPC
|4||LK4||Screen Refresh Rate ("1"=50Hz, "0"=60Hz)||Set to "1"=50Hz (but ignored by the KC BIOS, which always uses 50Hz even if LK4 is changed)
|-
|3||LK3|| rowspan="3" |3bit Distributor ID. Usually set to 4=[[Awa]], 5=[[Schneider]], or 7=[[Amstrad]], see See [[LK-selectable Brand Names]] for details.||Purpose unknown (set to "1")
|-
|2||LK2||Purpose unknown (set to "0")
|0||[[CRTC]] VSYNC||Vertical Sync ("1"=VSYNC active, "0"=VSYNC inactive)||Same as on CPC
|-
|}
{| class="wikitable"
|+ Distributor ID
!Bit 3
!Bit 2
!Bit 1
!Brand name
|-
|0
|0
|0
|Isp
|-
|0
|0
|1
|Triumph
|-
|0
|1
|0
|Saisho
|-
|0
|1
|1
|Solavox
|-
|1
|0
|0
|Awa
|-
|1
|0
|1
|Schneider
|-
|1
|1
|0
|Orion
|-
|1
|1
|1
|Amstrad
|}
* upper: output, lower: output
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|''!Bit''||''!Description''||''!Usage''
|-
|7||PSG BDIR(Bus DIRection)||rowspan=2|PSG function selection
|-
|6||PSG BC1||(Bus Control 1)
|-
|5||Cassette Write data||Cassette Out (sometimes also used as Printer Bit7, see [[8bit Printer Ports]])
|-
|3||rowspan=4|Keyboard line||rowspan=4|Select keyboard line to be scanned (0-15)
See [[Programming:Keyboard scanning]] for details
|-
|2
|}
{| class="wikitable"|+ [[PSG ]] function selection: {|{{Prettytable|width: 700px; font-size: 2em;}}|''!Bit 7''||''!Bit 6''||''!Function''
|-
|0||0||Inactive
In some of these modes, port C is used as a control/status port for port A or B. It can be used to confirm when data transfer may take place, and reflect any other flags. The 8255 PPI is therefore supplied with the added option for the user to set or reset any individual bits in port C.
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=== Mode 0 – Simple Input/output mode ===
[[File:8255 - mode-0.png]]
<br>
=== Mode 1 – Strobed Input/output or Handshake mode ===
[[File:8255 - mode-1.png]]
<br>
=== Mode 2 – Bidirectional Mode ===
[[File:8255 - mode-2.png]]
<br>
=== Port pins summary ===
[[File:8255 Block Diagram.png]]
The PPI 8255 does not have a clock pin. It relies purely on control signals from the CPU to operate. It uses Read, Write, and Control signals to manage data transfers instead of a clock signal. This allows it to work effectively without needing its own clock input.
<br>
* [[Media:Intel8255A_datasheet.pdf]] PPI Datasheet (Intel)
* [[Media:PPI M5L8255AP-5.pdf]] PPI Datasheet (Mitsubishi)
* [[Media:Programmable Peripheral Interface TMP8255AP-5.pdf]] PPI Datasheet (Toshiba)
* [https://github.com/jotego/jt8255 JT8255] Verilog implementation of the 8255 PPI