[[File:Amstrad 40007 Gate Array .png|right|thumb|Amstrad 40007 Gate Array]][[File:Amstrad 40010 Gate Array.png|right|thumb|Amstrad 40010 Gate Array]]
Also designated as Video gate Gate Array (VGA, not to be confused with the IBM PC compatible graphic card spec). <br>
== Introduction ==
The gate array Gate Array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.
In the CPC+ system, the functions of the Gate-Array are integrated into a single [[ASIC|ASIC]]. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate-Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.
In the [[KC Compact]] system, the functions of the Gate-Array are "emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.
In the "cost-down" version of the CPC6128, the functions of the Gate-Array are integrated into a an ASIC.
The Gate Array is described here is the one found in a standard CPC.<br>
== What does it do? ==
The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), bus arbitration, DRAM refresh, interrupt generation and memory arrangement.
== Interrupt management ==<br>
Interrupts on the CPC are created by the Gate Array based on settings from the CRTC. The Gate Array has an internal counter (R52) that counts from 0 to 51, incrementing after each HSYNC signal.== Bus arbitration ==
R52 will return to 0 and the The Gate Array will send an interrupt request on any of these conditions:* When it exceeds 51* By setting bit4 of arbitrates access to the RMR register of RAM between the CPU and the video hardware (CRTC and Gate -Array to 1* At the end of the 2nd HSYNC after the start of the VSYNC).
When the Gate Array sends an interrupt requestEvery microsecond:*If The CRTC generates a memory address using it's MA and RA signal outputs. See the interrupts were authorized at [[CRTC]] wiki page to know how the time of motherboard wiring transforms these signals into the request, then bit5 of R52 is cleared Video Memory Address (but R52 was reset to 0 anywayVMA) and the interrupt takes place.*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the The Gate Array then maintains its INT fetches 2 bytes for each address. /CPU_ADDR is a 1MHz signal). When interrupts So these 2 bytes are enabled (using fetched sequentially. They are not interleaved with Z80 access. These bytes are fetched even when the EI instruction) and '''after border is on as this is required for DRAM refresh.* The video hardware is given priority so that the instruction that follows EI''' (so display is not immediately after EI), bit5 of R52 is cleared and the interrupt takes placedisrupted.
== CSYNC ==The Gate-Array generates the "READY" signal which is connected to the "/WAIT" input signal of the CPU. This signal is used to stop the CPU accessing RAM while the video-hardware is accessing it.
On CPCIn fact, the HSYNC and VSYNC signals are received from the [[CRTC]]. These signals are then modified and merged by the Gate Array into a single CSYNC signal that will be sent allows the Z80 to access the displayRAM in only 1 out of every 4 cycles. As a result, all instruction timings are stretched so that they are all multiples of a microsecond (1µs), and this gives an effective CPU clock of 3.3Mhz.
When CRTC HSYNC Unlike the ZX Spectrum or the Amiga, where bus arbitration is activerestricted to the "contended memory" or "chip RAM", on the Gate-Array immediately outputs the palette colour blackCPC it also applies to ROM access and to RAM expansions. If So the HSYNC is set to 14 characters then black will be output for 14µsZ80 always runs at the same speed, regardless of the type of memory being accessed.
The HSYNC is modified before being sent Last but not least, bus arbitration also applies to the monitorI/O access. It only starts after 2µs and will last only a maximum of 4µsAnd memory access is not aligned with I/O access on Z80.
For exampleNote: On Amstrad Plus, if CRTC R2=46, and CRTC HSYNC width is 14 chars then monitor hsync starts at 48 and lasts only until 51 includedthe ASIC also has to handle DMA instruction fetch from RAM.
<br> == DRAM refresh == On Amstrad CPC, the Gate Array is responsible for the DRAM refresh, instead of using the Z80 built-in DRAM refresh mechanism. The VSYNC reason is that there can only be 3 DRAM accesses per microsecond on this architecture. Doing DRAM refresh on each M1 cycle as it is done on MSX would bog down the CPU speed on CPC given its bus arbitration scheme. The Z80 generates a maximum of one request per microsecond. The CPC also modified before being sent requires two memory accesses per microsecond for reading video data. The CPC specs 4164-20 DRAMs. These require 330nS for a read or write cycle. The CPC also uses the optimised sequential CAS cycles to read the monitor. It happens two lines* after video data bytes in half a microsecond. [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/the VSYNC -cpc-revision-zero-article/msg243769/ Source] The way to cause the RAM refresh to fail in both a Plus or normal CPC is simply to stop a few bits of the CRTC address changing (ie. never refresh the selected area). Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source] <br> == Interrupt generation ==[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)] The CPU maskable interrupts are generated by the Gate Array. This is done by using a 6bits internal counter and monitoring the HSync and VSync signals produced by the CRTC . On every falling edge of the HSync signal, the Gate Array will increment the counter by one. When the counter reaches 52, the Gate Array raise the INT signal and stay two lines reset the counter. With 50Hz PAL CRTC settings (same cut rule if VSYNC one HSync every 64us) this will produce a 300Hz interrupt rate. When the CPU acknowledge the interrupt (eg. it is lower going to jump to the interrupt vector), the Gate Array will reset bit5 of the counter, so the next interrupt can't occur closer than 432 HSync. When a VSync occurs, the Gate Array will wait for two HSync and: * If the counter>=32 (bit5=1), then no interrupt request is issued and counter is reset to 0. PAL * If the counter<32 (50Hzbit5=0) does need two lines VSYNC_width, then an interrupt request is issued and 4µs HSYNC_widthcounter is reset to 0. This 2 HSync delay after a VSync is used to let the main program, executed by the CPU, enough time to sense the VSync (for synchronisation with the display, most likely) before an interrupt service routine is eventually executed. So all the interrupt timings are mostly determined by the CRTC settings. Other than that, the internal interrupt counter can be cleared anytime by software using the Gate Array RMR register. The falling edge of the HSync trigger the counter, therefore modifying the duration of the HSync with the CRTC Register 3 can delay the interrupt requests by a few microseconds. This can be used to adjust interrupt timings between CPC and Plus machines… Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the [[ASIC]] wiki page. === Timings ===[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)] The INT signal (active low) produced by the Gate Array, is a short pulse of 1.4us and starts right after the falling edge of the HSync signal (produced by the CRTC).
The Gate Array uses 2 internal counters to create its CSYNC signal:=== DI in peace ===* H06 which counts the number of CRTC characters processed during an HSYNC* V26 which counts the number of HSYNCs occuring during a VSYNC[https://acpc.me/ACME/FANZINES Source: Amslive No4 (Madram)]
On a CPC monitorThe GA maintains its int request until it is accepted.RST #38 occurs not after the EI, but after the CSYNC is rendered in "absolute black"instruction following the EI (the Z80 needs time to clean up its act). It is darker than Even if the palette colour black output int isn't validated by the Gate ArrayZ80, IC (interrupt counter) continues on its merry way.But after the EI, a test similar to the one seen for the VBL is performed: The interrupt is generated anyway, but:* If IC < 32, IC is unchanged (the next int will then be produced 21 to 52 lines later).* Otherwise bit 5 of IC is set to zero.
== Controlling the Gate Array ==
The gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1".
The recommended I/O port address is &7Fxx.
The function to be performed Gate Array is selected by writing data not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. If you execute an I/O read operation on the Gate-ArrayI/O address, bit 7 and 6 of the data define the function selected (see table below). It is not possible to Gate Array will read an unpredictable value from the Gatedatabus which will be in high-impedance state. If the value is a valid Gate Arraycommand, it will be executed, otherwise nothing will happen. [https://www.grimware.org/doku. php/documentations/devices/gatearraydo=export_xhtml Source]
The function to be performed is selected by writing data to the Gate Array, the first bits of the data define the function selected (see table below). It is not possible to read from the Gate Array. {|{{Prettytableclass="wikitable"!colspan=4| 8bit command!rowspan=2| Machine!rowspan=2| Register!rowspan=2| Description!rowspan=2|width: 700px; font-size: 2em;}}Chip
|-
|''Data Bit ! 7''||''Data Bit ! 6''||''Function''! 5! 4..0
|-
| 0 || 0 || x || style="text-align: center;" | n || All || PENR || Select pena color register || Gate Array
|-
| 0 || 1 || Select colour for x || style="text-align: center;" | n || All || INKR || Change the value of the currently selected pencolor register || Gate Array
|-
| 1 || 0 || Select screen mode0 || style="text-align: center;" | n || All || RMR || Control Interrupt counter, ROM configuration mapping and interrupt controlGraphics mode || Gate Array
|-
| rowspan="2"| 1 || rowspan="2"|0 || rowspan="2"| 1 || RAM Memory Management style="text-align: center;" rowspan="2" | n || All || RMR || ''Ghost register'' || Gate Array (note 1CPC) or locked ASIC (Plus)
|-
| Plus || RMR2 || ASIC & Advanced ROM mapping || Unlocked ASIC
|-
| 1 || 1 ||colspan=2 style="text-align: center;" | n || All || MMR || RAM memory mapping || PAL (only with 128KB or RAM expansion)
|}
===== Note =====The MMR register is not available in the Gate Array, but is performed by a device at the same I/O port address location.
This function is not available in the Gate-Array, but is performed by a device at the same I/O port address location. In the CPC464, CPC664 and KC compact, this function MMR is performed in a an external memory-expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then the function MMR is not available. In the CPC6128, this function is performed by a [[PAL16L8|PAL]] located on the main PCB, or a memory-expansion. In the 464+ and 6128+ this function is performed by the ASIC or a memory expansion. Please read the document on RAM management for more information.
In the CPC6128, MMR is performed by a [[PAL16L8|PAL chip]] located on the main PCB, or an external memory expansion. In the 464+ and 6128+, MMR is performed by the ASIC or an external memory expansion. Please read the document on RAM management for more information. <br> == Registers == Note: The Plus palette capabilities are only accessible through the [[Default I/O Port Summary|ASIC I/O page]]. Registers PENR and INKR are not needed in that case. === Register 0 - Palette Index PENR (Pen selectionSelect a color register) ===
When bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.
Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens.
==== Summary ====
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit'' || ''!Value'' || ''!Function''
|-
| 7 || 0 || rowspan="2" | Gate Array function "Pen Selection"PENR register
|-
| 6 || 0
|}
<br> {|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-!Bit| ''Bit'' || ''!Value'' || ''!Function''
|-
| 7 || 0 || rowspan="2" | Gate Array function "Pen Selection"PENR register
|-
| 6 || 0
|}
<br> === Register 1 - Palette Data INKR (Colour selectionChange the value of the currently selected color register) ===
Once the pen has been selected its colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.
Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.
==== Summary ====
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit'' || ''!Value'' || ''!Function''
|-
| 7 || 0 || rowspan="2" | Gate Array function "Colour selection"INKR register
|-
| 6 || 1
|}
<br> === Register 2 - Select screen mode and RMR (Control Interrupt counter, ROM configuration mapping and Graphics mode) ===
This is a general purpose register responsible for the [[Video modes|screen graphics mode]] and the ROM configuration.
=== Screen = Graphics mode selection ====
The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit 1'' || ''!Bit 0'' || ''!Screen mode''
|-
| 0 || 0 || Mode 0, 160x200 resolution, 16 colours
Mode changing is synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC.
==== ROM configuration selection ====
Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the RAMROM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM.
Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &C000-&FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &c000-&ffff, will return data in the ROM. When data is written to &c000-&FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &c000-&ffff it will be the data in the RAM.
Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.
==== Summary ====
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"!Bit!Value!Function
|-
| ''Bit'' || ''Value'' || ''Function''|-| 7 || 1 || rowspan="2" | Gate Array functionRMR register
|-
| 6 || 0
|-
| 5 || - || not used''must be 0 on Plus machines with ASIC unlocked''
|-
| 4 || x || Interrupt generation control
| 2 || x || 1=Lower ROM area disable, 0=Lower ROM area enable
|-
| 1 || x || rowspan="2" | Screen Graphics Mode slectionselection
|-
| 0 || x
|}
<br> === Register 3 - RAM Banking RMR2 (ASIC & Advanced ROM mapping) ===
This register exists only in CPCs with 128K RAM (like the CPC 6128, Plus or CPCs with [[Standard Memory Expansions]]). Note: In the CPC 6128GX4000, and is only accessible when the register ASIC is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chipunlocked.
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"!Bit!Value!Function
|-
| ''Bit'' 7 || ''Value'' 1 || ''Function''rowspan="3" | Gate Array RMR2 register
|-
| 6 || 0|-| 5 || 1|-| 4 || x || rowspan="2" |RMR addressing mode|-| 3 || x|-| 2 || x || rowspan="3" | Physical ROM number (0..7)|-| 1 || x|-| 0 || x|} {| class="wikitable"|+ RMR addressing modes!Bit 4!Bit 3!Lower ROM![[ASIC|ASIC I/O page]]|-|0|0|&0000-&3FFF|Disabled|-|0|1|&4000-&7FFF|Disabled|-|1|0|&8000-&BFFF|Disabled|-|1|1|&0000-&3FFF|&4000-&7FFF|} The physical ROMs are also accessible as upper ROMs by using the [[Upper ROM Bank Number]] port and the RMR register. <br> === Register MMR (RAM memory mapping) === This register exists only in CPCs with 128K RAM (like the CPC 6128), or CPCs equipped with [[Standard Memory Expansions]]. Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip. {| class="wikitable"!Bit!Value!Function|-| 7 || 1 || rowspan="2" | Gate Array function 3MMR register
|-
| 6 || 1
|-
| 5 || b x || rowspan="3" |64K bank number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]]
|-
| 4 || bx
|-
| 3 || bx
|-
| 2 || x || rowspan="3" | RAM Config (0..7)
The Video RAM is always located in the first 64K, VRAM is in no way affected by this register.
<br>
== Programming the Gate Array - Examples ==
ret
</pre>
<br>
== Video memory structure ==
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|!rowspan=2|'''Graphics Mode'''||!colspan=8 style="text-align: center;"|'''VRAM byte'''||!colspan=8 style="text-align: center;"|'''Displayed Pixels'''!rowspan=2|Definition!rowspan=2|Pixel clock!rowspan=2|'''Definition'''Default resolution
|-
|'''!7'''|'''!6'''|'''!5'''|'''!4'''|'''!3'''|'''!2'''|'''!1'''|'''!0'''|'''!1'''|'''!2'''|'''!3'''|'''!4'''|'''!5'''|'''!6'''|'''!7'''|'''!8'''
|-
|0
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 16 colorscolours|4 MHz|160x200, 20-column text
|-
|1
|colspan=2 style="text-align: center;"|D
|4 pixels in 4 colours
|8 MHz
|320x200, 40-column text
|-
|2
|G
|H
|8 pixels in 2 colorscolours|16 MHz|640x200, 80-column text
|-
|3
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 4 colorscolours|4 MHz|160x200, 20-column text
|}
<br>
== Split rasters ==
To easily make split rasters compatible with both the CPC and the Plus machines, one can use the ASIC soft-scroll control register (SSCR) to finely adjust the horizontal position of the graphics.
<br>
== Palette R,G,B definitions ==
To display a CPC image you will need to use a analogue monitor with a composite sync.
<br> === Palette sorted by Hardware Firmware Colour Numbers === The firmware colour palette is sorted by luminance value.
{| class="FCK__ShowTableBorderswikitable"
|-
| ''Hardware Number||Firmware Number|| ''Colour Name''
| ''R %'' || ''G %'' || ''B %'' || ''Colour''
|-
| 0 (40h) || 13 || White || 50|| 50|| 50|| bgcolor="#808080" | !Firmware Number!Hardware Number!Colour Name!R %!G %!B %!ASIC!Colour
|-
| 1 (41h) 0|| (13) 54h || White Black || 50 0|| 50 0|| 50 0|| #000|| bgcolor="#808080000000" |
|-
| 2 1|| 44h (42hor 50h) || 19 Blue || Sea Green 0|| 0||10050|| 50#006|| bgcolor="#00ff80000080" |
|-
| 3 (43h) 2|| 25 55h || Pastel Yellow Bright Blue ||100 0|| 0||100|| 50#00F|| bgcolor="#ffff800000ff" |
|-
| 4 (44h) 3|| 1 5Ch || Blue Red || 50|| 0|| 0|| 50#600|| bgcolor="#000080800000" |
|-
| 5 (45h) 4|| 7 58h || Purple Magenta ||10050|| 0|| 50|| #606|| bgcolor="#ff0080800080" |
|-
| 6 (46h) 5|| 10 5Dh || Cyan Mauve || 50|| 0|| 50100|| 50#60F|| bgcolor="#0080808000ff" |
|-
| 7 (47h) 6|| 16 4Ch || Pink Bright Red ||100|| 50 0|| 50 0|| #F00|| bgcolor="#ff8080ff0000" |
|-
| 8 (48h) 7|| 45h (7or 48h) || Purple ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" |
|-
| 9 (49h) 8|| (25) 4Dh || Pastel Yellow Bright Magenta ||100|| 0||100|| 50#F0F|| bgcolor="#ffff80ff00ff" |
|-
| 10 (4Ah) 9|| 24 56h || Bright Yellow Green ||100 0||10050|| 0|| #060|| bgcolor="#ffff00008000" |
|-
| 11 (4Bh) 10|| 26 46h ||Cyan || Bright White 0||10050||10050||100#066|| bgcolor="#ffffff008080" |
|-
| 12 (4Ch) 11|| 6 57h || Bright Red ||100Sky Blue || 0|| 050||100|| #06F|| bgcolor="#ff00000080ff" |
|-
| 13 (4Dh) 12|| 8 5Eh || Bright MagentaYellow ||10050|| 50|| 0||100#660|| bgcolor="#ff00ff808000" |
|-
| 14 13|| 40h (4Ehor 41h) || 15 White || Orange 50||10050|| 50|| 0#666|| bgcolor="#ff8000808080" |
|-
| 15 (4Fh) 14|| 17 5Fh || Pastel MagentaBlue ||10050|| 50||100|| #66F|| bgcolor="#ff80ff8080ff" |
|-
| 16 (50h) 15|| (1) 4Eh || Blue Orange || 0100|| 50|| 0|| 50#F60|| bgcolor="#000080ff8000" |
|-
| 17 (51h) 16|| (19) 47h || Sea Green Pink || 0100||10050|| 50|| #F66|| bgcolor="#00ff80ff8080" |
|-
| 18 (52h) 17|| 18 4Fh || Bright Green Pastel Magenta || 0100|| 50||100|| 0#F6F|| bgcolor="#00ff00ff80ff" |
|-
| 19 (53h) 18|| 20 52h || Bright Cyan Green || 0||100||100 0|| #0F0|| bgcolor="#00ffff00ff00" |
|-
| 20 19|| 42h (54hor 51h) || 0 || Black Sea Green || 0|| 0100|| 050|| #0F6|| bgcolor="#00000000ff80" |
|-
| 21 (55h) 20|| 2 53h || Bright Blue Cyan || 0|| 0100||100|| #0FF|| bgcolor="#0000ff00ffff" |
|-
| 22 (56h) 21|| 9 5Ah || Green Lime || 050|| 50100|| 0|| #6F0|| bgcolor="#00800080ff00" |
|-
| 23 (57h) 22|| 11 59h ||Pastel Green || Sky Blue 50|| 0100|| 50||100#6F6|| bgcolor="#0080ff80ff80" |
|-
| 24 (58h) 23|| 4 5Bh || Magenta Pastel Cyan || 50|| 0100|| 50100|| #6FF|| bgcolor="#80008080ffff" |
|-
| 25 (59h) 24|| 22 4Ah || Pastel Green Bright Yellow || 50100||100|| 50 0|| #FF0|| bgcolor="#80ff80ffff00" |
|-
| 26 25|| 43h (5Ahor 49h) || 21 Pastel Yellow || Lime 100|| 50100||10050|| 0#FF6|| bgcolor="#80ff00ffff80" |
|-
| 27 (5Bh) 26|| 23 4Bh || Pastel Cyan Bright White || 50100||100||100|| #FFF|| bgcolor="#80ffffffffff" | |} Note: We can observe that the official Amstrad names of some colours are a bit silly: "red" is in fact brown, "yellow" is in fact khaki and "white" is in fact grey. <br> === Amstrad Colour Names === <gallery>Cpc 6128 master colour chat.jpg|Master colour chartCpc 6128 farbtabelle.jpg|FarbtabelleCpc 6128 palette des couleurs.jpg|Palette des couleursCpc 6128 tabla de colores.jpg|Tabla de colores</gallery> <br> === Palette sorted by Hardware Colour Numbers === {| class="wikitable"
|-
| 28 (5Ch) || 3 || Red || 50|| 0|| 0|| bgcolor="#800000" | !Hardware Number!Firmware Number!R %!G %!B %!ASIC!Colour!Colour Name!German Name!French Name!Spanish Name
|-
| 29 0 (5Dh40h) || 5 13 || Mauve 50|| 50|| 050||100#666|| bgcolor="#8000ff808080" | || White || Weiß || Blanc || Blanco
|-
| 30 1 (5Eh41h) || 12 (13) || Yellow 50|| 50|| 50|| 0#666|| bgcolor="#808000808080" | || White || Weiß || Blanc || Blanco
|-
| 31 2 (5Fh42h) || 14 19 || Pastel Blue 0|| 50100|| 50||100#0F6|| bgcolor="#8080ff00ff80" | |} === Palette sorted by Firmware Colour Numbers === {| class="FCK__ShowTableBorders"Sea Green || Seegrün || Vert marin || Verde marino
|-
| ''Firmware Number'' 3 (43h) || ''Hardware Number'' 25 || ''Colour Name'' 100| ''R %'' |100| ''G %'' |50| ''B %'' |#FF6| ''Colour''| bgcolor="#ffff80" | || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 0 4 (44h) || 54h ||Black 1 || 0|| 0|| 050|| #006||bgcolor="#000000000080"||| Blue || Blau || Bleu || Azul
|-
| 1|| 44h 5 (or 50h45h) ||Blue 7 || 0100|| 0|| 50|| #F06||bgcolor="#000080ff0080"||| Purple || Purpur || Pourpre || Púrpura
|-
| 2 6 (46h) || 55h ||Bright Blue 10 || 0|| 050||10050|| #066||bgcolor="#0000ff008080"||| Cyan || Blaugrün || Turquoise || Ciano
|-
| 3 7 (47h) || 5Ch 16 ||Red 100|| 50|| 050|| 0#F66||bgcolor="#800000ff8080"||| Pink || Rosa || Rose || Rosa
|-
| 4 8 (48h) || 58h (7) ||Magenta || 50100|| 0|| 50|| #F06||bgcolor="#800080ff0080"||| Purple || Purpur || Pourpre || Púrpura
|-
| 5 9 (49h) || 5Dh (25) ||Mauve 100|| 50100|| 050||100#FF6||bgcolor="#8000ffffff80"||| Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 610 (4Ah) || 4Ch 24 ||Bright Red 100||100|| 0|| 0#FF0||bgcolor="#ff0000ffff00"||| Bright Yellow || Hellgelb || Jaune vif || Amarillo brillante
|-
| 7|| 45h 11 (or 48h4Bh) ||Purple 26 ||100|| 0100|| 50100|| #FFF||bgcolor="#ff0080ffffff"||| Bright White || Leuchtendweiß || Blanc brillant || Blanco brillante
|-
| 812 (4Ch) || 4Dh 6 ||Bright Magenta 100||100 0|| 0||100#F00||bgcolor="#ff00ffff0000"||| Bright Red || Hellrot || Rouge vif || Rojo brillante
|-
| 913 (4Dh) || 56h 8 ||Green 100|| 0|| 50100|| 0#F0F||bgcolor="#008000ff00ff"||| Bright Magenta|| helles Magenta || Magenta vif || Magenta brillante
|-
|1014 (4Eh) || 46h 15 ||Cyan 100|| 50|| 0|| 50|| 50#F60||bgcolor="#008080ff8000"||| Orange || Orange || Orange || Naranja
|-
|1115 (4Fh) || 57h 17 ||Sky Blue || 0100|| 50||100|| #F6F||bgcolor="#0080ffff80ff"||| Pastel Magenta|| Pastell-magenta || Magenta pastel || Magenta pastel
|-
|1216 (50h) || 5Eh (1) ||Yellow 0|| 50 0|| 50|| 0#006||bgcolor="#808000000080"||| Blue || Blau || Bleu || Azul
|-
|1317 (51h) || 40h (or 41h19) ||White 0|| 50100|| 50|| 50#0F6||bgcolor="#80808000ff80"||| Sea Green || Seegrün || Vert marin || Verde marino
|-
|1418 (52h) || 5Fh 18 ||Pastel Blue 0|| 50100|| 50 0||100#0F0||bgcolor="#8080ff00ff00"||| Bright Green || Hellgrün || Vert vif || Verde brillante
|-
|1519 (53h) || 4Eh 20 ||Orange 0||100|| 50100|| 0#0FF||bgcolor="#ff800000ffff"||| Bright Cyan || helles Blaugrün || Turquoise vif || Ciano brillante
|-
|1620 (54h) || 47h 0 ||Pink 0||100 0|| 50 0|| 50#000||bgcolor="#ff8080000000"||| Black || Schwarz || Noir || Negro
|-
|1721 (55h) || 4Fh 2 ||Pastel Magenta 0||100 0|| 50100||100#00F||bgcolor="#ff80ff0000ff"||| Bright Blue || Hellblau || Bleu vif || Azul brillante
|-
|1822 (56h) || 52h ||Bright Green 9 || 0||10050|| 0|| #060||bgcolor="#00ff00008000"||| Green || Grün || Vert || Verde
|-
|19|| 42h 23 (or 51h57h) ||Sea Green 11 || 0|| 50||100|| 50#06F||bgcolor="#00ff800080ff"||| Sky Blue || Himmelblau || Bleu ciel || Azul cielo
|-
|2024 (58h) || 53h 4 ||Bright Cyan 50|| 0||10050||100#606||bgcolor="#00ffff800080"||| Magenta || Magenta || Magenta || Magenta
|-
|2125 (59h) || 5Ah ||Lime 22 || 50||100|| 050|| #6F6||bgcolor="#80ff0080ff80"||| Pastel Green || Pastellgrün || Vert pastel || Verde pastel
|-
|2226 (5Ah) || 59h ||Pastel Green 21 || 50||100|| 50 0|| #6F0||bgcolor="#80ff8080ff00"||| Lime || Limonengrün || Vert citron || Verde lima
|-
|23|| 27 (5Bh ) ||Pastel Cyan 23 || 50||100||100|| #6FF||bgcolor="#80ffff"||| Pastel Cyan || Pastell-blaugrün|| Turquoise pastel|| Ciano pastel
|-
|2428 (5Ch) || 4Ah 3 ||Bright Yellow 50||100||100 0|| 0|| #600||bgcolor="#ffff00800000"||| Red || Rot || Rouge || Rojo
|-
|25|| 43h 29 (or 49h5Dh) ||Pastel Yellow 5 ||10050|| 0||100|| 50#60F||bgcolor="#ffff808000ff"||| Mauve || Hellviolett || Mauve || Malva
|-
|2630 (5Eh) || 4Bh 12 || 50|| 50|| 0|| #660|| bgcolor="#808000" | || Yellow || Gelb || Jaune || Amarillo|-| 31 (5Fh) ||Bright White 14 ||10050||10050||100|| #66F||bgcolor="#ffffff8080ff"||| Pastel Blue || Pastellblau || Bleu pastel || Azul pastel
|}
<br>
=== Intensities ===
The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).
On an actual Amstrad CPC, the half-intensity colour signal is measured to be closer to 40% rather than the expected 50%. This was verified by [[Grim]] and independently confirmed by [[Nocash]]. [https://www.grimware.org/doku.php/documentations/devices/gatearray#inkr Source]
* [[CPC Palette]] - some more details
=== To calculate This explains why the Amstrad engineers used the following values to adapt the old colour palette to the new 12-bit palette on the Amstrad Plus:* 0% became #0* 50% became #6. They specifically chose #6 for the 50% value ===instead of the expected #7 or #8, to better match the real Amstrad CPC palette.* 100% became #F
'''Red''' <br>
0% => do not add anything == Green Screen Colours ===
50% => add 3 On a green screen, where all colours are shades of unsaturated green, the firmware colours are in order of increasing intensity. Black is darkest green, bright white is brightest green, and firmware colour 13 is a medium green.
100% => add The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. Amstrad preferred to propose a completely different image system, not comparable to a conversion to monochrome, which would have limited the number of brightness levels to 21 (for example, colours 9 and 6 would have had the same luminance).
'''Green''' They opted for a table of 27 linear brightness steps. They assigned values of 1 (1kΩ) for blue, 3 (3.3kΩ) for red, and 9 (10kΩ) for green.
0% => do not add anything === To calculate the luminance value ====
50% => add 9 '''Red'''
*0% => do not add anything *50% => add 3 *100% => add 18 6
'''BlueGreen'''
*0% => do not add anything *50% => add 9 *100% => add 18
50% => add 1 '''Blue'''
*0% => do not add anything *50% => add 1 *100% => add 2
=== Green Screen Colours === On a green screen (where all colours are shades of green), the colours (in the software/firmware colours), are in order of increasing intensity. Black is very dark, and white is bright green, and colour 13 is a medium green. (Thanks to [[Mark Rison|Mark Rison]] for this information)<br>
== Pictures ==
</gallery>
==See also==[[File:Ga.pinout.40007.png]] [[File:Ga.pinout.40008.40010.png]]
*[[Note: Some CPC motherboards can accommodate both types of Gate Array and ASIC Pinpinouts. [https://thecheshirec.at/2024/10/06/il-existe-une-carte-multi-gate-array-et-cest-amstrad-qui-la-Outs]faite/ Source]
*[[Video modes]] : for other informations on colours and pixels.<br>
== External links ==*[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]* [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Gate Array documentation in Amstrad CRTCCompendium]* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware] * [http: the other video stuff//quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)] <br> ==See also== *[[Gate Array and ASIC Pin-Outs]]*[[PAL16L8]] : for RAM arrangement
*[[ASIC]] : for Plus users
*[[CRTC]] : the other video stuff
*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.
*[[Video modes]] : for other informations on colours and pixels.
*[[Media:40010-simplified V03.pdf]] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Forum thread] Gate Array schematics - reverse engineered by Gerald
== External links ==
*[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]
* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]
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