[[File:Amstrad 40007 Gate Array .png|right|thumb|Amstrad 40007 Gate Array]][[File:Amstrad 40010 Gate Array.png|right|thumb|Amstrad 40010 Gate Array]]
Also designated as Video gate Gate Array (VGA, not to be confused with the IBM PC compatible graphic card spec).
<br>
In the [[KC Compact]] system, the functions of the Gate Array are "emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.
In the "cost-down" version of the CPC6128, the functions of the Gate Array are integrated into a an ASIC.
<br>
== DRAM refresh ==
On Amstrad CPC, the Gate Array is responsible for the DRAM refresh , instead of using the Z80 built-in DRAM refresh mechanism. The reason is that there can only be 3 DRAM accesses per microsecond on this architecture. Doing DRAM refresh on each M1 cycle as it is done on MSX would bog down the CPU speed on CPC given its bus arbitration scheme.
The Z80 generates a maximum of one request per microsecond. The CPC also requires two memory accesses per microsecond for reading video data.
== Interrupt generation ==
[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)]
Interrupts on the CPC The CPU maskable interrupts are created generated by the Gate Array based on settings from the CRTC. The Gate Array has an This is done by using a 6bits internal counter R52 (and monitoring the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signalHSync and VSync signals produced by the CRTC.
On all CRTCsevery falling edge of the HSync signal, R52 interrupts always start 1µs after the end of an HSYNCGate Array will increment the counter by one. But on CRTCs 3/4When the counter reaches 52, HSYNCs occur 1µs later than on CRTCs 0/1/2the Gate Array raise the INT signal and reset the counter. Which means that on CRTCs 3/4, interrupts start 1µs later than on CRTCs 0/1/2With 50Hz PAL CRTC settings (one HSync every 64us) this will produce a 300Hz interrupt rate.
R52 will return to 0 and When the CPU acknowledge the Gate Array will send an interrupt request on any of these conditions:* When (eg. it exceeds 51* By setting bit4 of is going to jump to the RMR register of interrupt vector), the Gate Array to 1* At the end will reset bit5 of the 2nd HSYNC after counter, so the start of the VSYNCnext interrupt can't occur closer than 32 HSync.
When the Gate Array sends an interrupt request:*If the interrupts were authorized at the time of the requesta VSync occurs, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction), bit5 of R52 is cleared will wait for two HSync and the interrupt takes place. This happens only '''after the instruction that follows EI''' as this Z80 instruction has a 1-instruction delay.:
Note: On Amstrad Plus, * If the counter>=32 (bit5=1), then no interrupt management system request is seriously beefed upissued and counter is reset to 0. See * If the [[ASIC]] wiki pagecounter<32 (bit5=0), then an interrupt request is issued and counter is reset to 0.
<br>This 2 HSync delay after a VSync is used to let the main program, executed by the CPU, enough time to sense the VSync (for synchronisation with the display, most likely) before an interrupt service routine is eventually executed.
== CSYNC signal ==So all the interrupt timings are mostly determined by the CRTC settings. Other than that, the internal interrupt counter can be cleared anytime by software using the Gate Array RMR register.
The HSYNC and VSYNC signals are received from falling edge of the HSync trigger the counter, therefore modifying the duration of the HSync with the [[CRTC]]. These signals are then modified Register 3 can delay the interrupt requests by the Gate Array to C-HSYNC and C-VSYNC and merged into a single CSYNC signal that will few microseconds. This can be sent used to the display.adjust interrupt timings between CPC and Plus machines…
When CRTC HSYNC is activeNote: On Amstrad Plus, the Gate Array immediately outputs the palette colour blackinterrupt management system is seriously beefed up. If See the HSYNC is set to 14 characters then black will be output for 14µs[[ASIC]] wiki page.
If a graphics mode change is pending, the HSYNC pulse width needs to be at least 2µs for Gate Array to change the graphics mode=== Timings ===[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)]
C-HSYNC begins 2µs after activation of The INT signal (active low) produced by the CRTC HSYNC and stays Gate Array, is a maximum short pulse of 4µs (1.4us and starts right after the falling edge of the HSync signal is cut short if HSYNC width is greater than 6(produced by the CRTC).
For example, if CRTC R2=46, and CRTC HSYNC width is 14 chars then C-HSYNC starts at 48 and lasts only until 51 included== DI in peace ===[https://acpc.me/ACME/FANZINES Source: Amslive No4 (Madram)]
On Gate Array, even if the duration of the CRTC VSYNC The GA maintains its int request until it is reduced to 2 µseconds, accepted.RST #38 occurs not after the Gate Array will always output black for 26 lines with 4 lines of C-VSYNC to the monitor. While on ASIC/Pre-ASICEI, but after the CRTC VSYNC must be active as long as instruction following the C-VSYNC signal is sent to EI (the monitor. The Gate Array (and ASIC/Pre-ASIC) uses 2 internal counters Z80 needs time to create clean up its CSYNC signal:* H06 counts act). Even if the number of CRTC characters processed during an HSYNC. H06 is incremented int isn't validated by the Gate Array for each CRTC character when CRTC HSYNC is active. The Gate Array activates the C-HSYNC signal when H06 reaches 2Z80, and changes IC (interrupt counter) continues on its graphics mode if a change was pending. It deactivates this signal when H06 reaches 6merry way.* V26 counts But after the number of HSYNCs occuring during EI, a VSYNC. V26 is incremented by test similar to the Gate Array when one seen for the CRTC signals an end of HSYNC. VBL is performed: The Gate Array activates the C-VSYNC signal when V26 reaches 2 (and if VSYNC interrupt is active on ASIC/Pre-ASIC). It deactivates this signal when V26 reaches 6. After the 26th line has been processedgenerated anyway, the Gate Array stops outputting the palette colour black.but:* If CRTC VSYNC is activated again while V26 is still in progressIC < 32, then V26 IC is reset to 0 and starts counting up again unchanged (the HSYNC pulses. The HSYNC signal from the CRTC is 0 when inactive and 1 when active. Same for VSYNC. C-HSYNC and C-VSYNC are composited using the XNOR function. The resulting CSYNC signal next int will then be produced by the Gate Array is 1 when inactive and 0 when active21 to 52 lines later). On a CPC monitor, the CSYNC * Otherwise bit 5 of IC is rendered in "absolute black"set to zero. It is darker than the palette colour black output by the Gate Array. The electron beam is basically turned off. Turning up the brightness level won't make it any brighter. <br>
== Controlling the Gate Array ==
The recommended I/O port address is &7Fxx.
The Gate Array is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. If you execute an I/O read operation on the Gate Array I/O address, the Gate Array will read an unpredictable value from the databus which will be in high-impedance state. If the value is a valid Gate Array command, it will be executed, otherwise nothing will happen. [https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml Source]
The function to be performed is selected by writing data to the Gate Array, the first bits of the data define the function selected (see table below). It is not possible to read from the Gate Array.
| 1 || 0 || 0 || style="text-align: center;" | n || All || RMR || Control Interrupt counter, ROM mapping and Graphics mode || Gate Array
|-
| rowspan="2"| 1 || rowspan="2"| 0 || rowspan="2"| 1 || style="text-align: center;" rowspan="2" | n || All || RMR || ''Ghost register'' || Gate Array (CPC) or locked ASIC (Plus)
|-
| 1 || 0 || 1 || style="text-align: center;" | n || Plus || RMR2 || ASIC & Advanced ROM mapping || Unlocked ASIC
|-
| 1 || 1 ||colspan=2 style="text-align: center;" | n || All || MMR || RAM memory mapping || PAL(only with 128KB or RAM expansion)
|}
In the CPC464, CPC664 and KC compact, MMR is performed in an external memory expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then MMR is not available.
In the CPC6128, MMR is performed by a [[PAL16L8|PALchip]] located on the main PCB, or an external memory expansion.
In the 464+ and 6128+, MMR is performed by the ASIC or an external memory expansion. Please read the document on RAM management for more information.
==== ROM configuration selection ====
Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the RAMROM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM.
Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &C000-&FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &c000-&ffff, will return data in the ROM. When data is written to &c000-&FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &c000-&ffff it will be the data in the RAM.
Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.
==== Summary ====
| 5 || 1
|-
| 4 || x || rowspan="2" |Lower ROM address and ASIC I/O page RMR addressing mode
|-
| 3 || x
|}
The lower {| class="wikitable"|+ RMR addressing modes!Bit 4!Bit 3!Lower ROM address and ![[Default I/O Port SummaryASIC|ASIC I/O page]] modes are: |-Mode- ROM address ASIC I/O Page 00 |0|0|&0000-&3FFF |Disabled 01 |-|0|1|&4000-&7FFF |Disabled 10 |-|1|0|&8000-&BFFF |Disabled 11 |-|1|1|&0000-&3FFF |&4000-&7fff7FFF|}
The physical ROMs are also accessible as upper ROMs by using the [[Upper ROM Bank Number]] port and the RMR register.
=== Register MMR (RAM memory mapping) ===
This register exists only in CPCs with 128K RAM (like the CPC 6128), or CPCs equipped with [[Standard Memory Expansions]]). Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip. See its wiki page.
{| class="wikitable"
!colspan=8|Displayed Pixels
!rowspan=2|Definition
!rowspan=2|Pixel clock
!rowspan=2|Default resolution
|-
!7
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 16 colorscolours|4 MHz|160x200, 20-column text
|-
|1
|colspan=2 style="text-align: center;"|D
|4 pixels in 4 colours
|8 MHz
|320x200, 40-column text
|-
|2
|G
|H
|8 pixels in 2 colorscolours|16 MHz|640x200, 80-column text
|-
|3
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 4 colorscolours|4 MHz|160x200, 20-column text
|}
<br>
=== Palette sorted by Hardware Firmware Colour Numbers ===
The firmware colour palette is sorted by luminance value. {| class="FCK__ShowTableBorderswikitable"
|-
| ''Hardware Number||Firmware Number|| ''Colour Name''
| ''R %'' || ''G %'' || ''B %'' || ''ASIC'' || ''Colour''
|-
| 0 (40h) || 13 || White || 50|| 50|| 50|| #666|| bgcolor="#808080" | !Firmware Number!Hardware Number!Colour Name!R %!G %!B %!ASIC!Colour
|-
| 1 (41h) 0|| (13) 54h || White Black || 50 0|| 50 0|| 50 0|| #666000|| bgcolor="#808080000000" |
|-
| 2 1|| 44h (42hor 50h) || 19 || Sea Green Blue || 0||100 0|| 50|| #0F6006|| bgcolor="#00ff80000080" |
|-
| 3 (43h) 2|| 25 55h || Pastel Yellow Bright Blue ||100 0||100 0|| 50100|| #FF600F|| bgcolor="#ffff800000ff" |
|-
| 4 (44h) 3|| 1 5Ch || Blue Red || 50|| 0|| 0|| 50|| #006600|| bgcolor="#000080800000" |
|-
| 5 (45h) 4|| 7 58h || Purple Magenta ||10050|| 0|| 50|| #F06606|| bgcolor="#ff0080800080" |
|-
| 6 (46h) 5|| 10 5Dh || Cyan Mauve || 50|| 0|| 50|| 50100|| #06660F|| bgcolor="#0080808000ff" |
|-
| 7 (47h) 6|| 16 4Ch || Pink Bright Red ||100|| 50 0|| 50 0|| #F66F00|| bgcolor="#ff8080ff0000" |
|-
| 8 (48h) 7|| 45h (7or 48h) || Purple ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" |
|-
| 9 (49h) 8|| (25) 4Dh || Pastel Yellow Bright Magenta ||100||100 0|| 50100|| #FF6F0F|| bgcolor="#ffff80ff00ff" |
|-
| 10 (4Ah) 9|| 24 56h || Bright Yellow Green ||100 0||10050|| 0|| #FF0060|| bgcolor="#ffff00008000" |
|-
| 11 (4Bh) 10|| 26 46h || Bright White Cyan ||100 0||10050||10050|| #FFF066|| bgcolor="#ffffff008080" |
|-
| 12 (4Ch) 11|| 6 57h || Bright Red ||100Sky Blue || 0|| 050||100|| #F0006F|| bgcolor="#ff00000080ff" |
|-
| 13 (4Dh) 12|| 8 5Eh || Bright MagentaYellow ||10050|| 050||100 0|| #F0F660|| bgcolor="#ff00ff808000" |
|-
| 14 13|| 40h (4Ehor 41h) || 15 White || Orange ||10050|| 50|| 050|| #F60666|| bgcolor="#ff8000808080" |
|-
| 15 (4Fh) 14|| 17 5Fh || Pastel MagentaBlue ||10050|| 50||100|| #F6F66F|| bgcolor="#ff80ff8080ff" |
|-
| 16 (50h) 15|| (1) 4Eh || Blue Orange || 0100|| 50|| 0|| 50|| #006F60|| bgcolor="#000080ff8000" |
|-
| 17 (51h) 16|| (19) 47h || Sea Green Pink || 0100||10050|| 50|| #0F6F66|| bgcolor="#00ff80ff8080" |
|-
| 18 (52h) 17|| 18 4Fh || Bright Green Pastel Magenta || 0100||10050|| 0100|| #0F0F6F|| bgcolor="#00ff00ff80ff" |
|-
| 19 (53h) 18|| 20 52h || Bright Cyan Green || 0||100||100 0|| #0FF0F0|| bgcolor="#00ffff00ff00" |
|-
| 20 19|| 42h (54hor 51h) || 0 || Black Sea Green || 0|| 0100|| 050|| #0000F6|| bgcolor="#00000000ff80" |
|-
| 21 (55h) 20|| 2 53h || Bright Blue Cyan || 0|| 0100||100|| #00F0FF|| bgcolor="#0000ff00ffff" |
|-
| 22 (56h) 21|| 9 5Ah || Green Lime || 050|| 50100|| 0|| #0606F0|| bgcolor="#00800080ff00" |
|-
| 23 (57h) 22|| 11 59h || Sky Blue || 0Pastel Green || 50||100|| 50|| #06F6F6|| bgcolor="#0080ff80ff80" |
|-
| 24 (58h) 23|| 4 5Bh || Magenta Pastel Cyan || 50|| 0100|| 50100|| #6066FF|| bgcolor="#80008080ffff" |
|-
| 25 (59h) 24|| 22 4Ah || Pastel Green Bright Yellow || 50100||100|| 50 0|| #6F6FF0|| bgcolor="#80ff80ffff00" |
|-
| 26 (5Ah) || 21 || Lime || 50||100|| 0|| #6F0|| bgcolor="#80ff00" | 25|-| 27 43h (5Bhor 49h) || 23 || Pastel Cyan || 50Yellow ||100||100|| #6FF|| bgcolor="#80ffff" | |-| 28 (5Ch) || 3 || Red || 50|| 0|| 0|| #600FF6||bgcolor="#800000ffff80" |
|-
| 29 (5Dh) 26|| 5 4Bh || Mauve Bright White || 50|| 0100||100|| #60F||bgcolor="#8000ff" | |-| 30 (5Eh) || 12 || Yellow || 50|| 50|| 0|| #660||bgcolor="#808000" | |-| 31 (5Fh) || 14 || Pastel Blue || 50|| 50||100|| #66FFFF||bgcolor="#8080ffffffff" |
|}
Note: We can observe that the official Amstrad names of some colours are a bit silly: "red" is in fact brown, "yellow" is in fact khaki and "white" is in fact grey.
<br>
=== Palette sorted by Firmware Amstrad Colour Numbers Names ===
<gallery>Cpc 6128 master colour chat.jpg|Master colour chartCpc 6128 farbtabelle.jpg|FarbtabelleCpc 6128 palette des couleurs.jpg|Palette des couleursCpc 6128 tabla de colores.jpg|Tabla de colores</gallery> <br> === Palette sorted by Hardware Colour Numbers === {| class="FCK__ShowTableBorderswikitable"
|-
| ''Firmware Number'' || ''!Hardware Number'' || ''Colour Name'' | ''!Firmware Number!R %'' || ''!G %'' || ''!B %'' || ''!ASIC'' || ''!Colour''!Colour Name!German Name!French Name!Spanish Name
|-
| 0(40h) || 54h 13 ||Black 50|| 050|| 0|| 050|| #000666||bgcolor="#000000808080"||| White || Weiß || Blanc || Blanco
|-
| 1(41h) || 44h (or 50h13) ||Blue 50|| 0|| 050|| 50|| #006666||bgcolor="#000080808080"||| White || Weiß || Blanc || Blanco
|-
| 2(42h) || 55h ||Bright Blue 19 || 0|| 0100||10050|| #00F0F6||bgcolor="#0000ff00ff80"||| Sea Green || Seegrün || Vert marin || Verde marino
|-
| 3(43h) || 5Ch 25 ||Red 100|| 50100|| 0|| 050|| #600FF6||bgcolor="#800000ffff80"||| Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 4(44h) || 58h 1 ||Magenta || 50 0|| 0|| 50|| #606006||bgcolor="#800080000080"||| Blue || Blau || Bleu || Azul
|-
| 5(45h) || 5Dh 7 ||Mauve || 50100|| 0||10050|| #60FF06||bgcolor="#8000ffff0080"||| Purple || Purpur || Pourpre || Púrpura
|-
| 6(46h) || 4Ch ||Bright Red ||10010 || 0|| 050|| 50|| #F00066||bgcolor="#ff0000008080"||| Cyan || Blaugrün || Turquoise || Ciano
|-
| 7|| 45h (or 48h47h) ||Purple 16 ||100|| 050|| 50|| #F06F66||bgcolor="#ff0080ff8080"||| Pink || Rosa || Rose || Rosa
|-
| 8(48h) || 4Dh ||Bright Magenta (7) ||100|| 0||10050|| #F0FF06||bgcolor="#ff00ffff0080"||| Purple || Purpur || Pourpre || Púrpura
|-
| 9(49h) || 56h (25) ||Green 100|| 0100|| 50|| 0|| #060FF6||bgcolor="#008000ffff80"||| Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
|10(4Ah) || 46h 24 ||Cyan 100||100|| 0|| 50|| 50|| #066FF0||bgcolor="#008080ffff00"||| Bright Yellow || Hellgelb || Jaune vif || Amarillo brillante
|-
|11(4Bh) || 57h 26 ||Sky Blue 100|| 0|| 50100||100|| #06FFFF||bgcolor="#0080ffffffff"||| Bright White || Leuchtendweiß || Blanc brillant || Blanco brillante
|-
|12(4Ch) || 5Eh 6 ||Yellow 100|| 50|| 50 0|| 0|| #660F00||bgcolor="#808000ff0000"||| Bright Red || Hellrot || Rouge vif || Rojo brillante
|-
|13|| 40h (or 41h4Dh) ||White 8 || 50100|| 50 0|| 50100||#666F0F||bgcolor="#808080ff00ff"||| Bright Magenta|| helles Magenta || Magenta vif || Magenta brillante
|-
|14(4Eh) || 5Fh 15 ||Pastel Blue 100|| 50|| 50||100 0|| #66FF60||bgcolor="#8080ffff8000"||| Orange || Orange || Orange || Naranja
|-
|15(4Fh) || 4Eh ||Orange 17 ||100|| 50|| 0100|| #F60F6F|| bgcolor="#ff8000ff80ff"||| Pastel Magenta|| Pastell-magenta || Magenta pastel || Magenta pastel
|-
|16(50h) || 47h (1) ||Pink 0||100|| 50 0|| 50|| #F66006||bgcolor="#ff8080000080"||| Blue || Blau || Bleu || Azul
|-
|17(51h) || 4Fh (19) ||Pastel Magenta 0||100|| 50||100|| #F6F0F6||bgcolor="#ff80ff00ff80"||| Sea Green || Seegrün || Vert marin || Verde marino
|-
|18|| (52h ) ||Bright Green 18 || 0||100|| 0|| #0F0||bgcolor="#00ff00"||| Bright Green || Hellgrün || Vert vif || Verde brillante
|-
|19|| 42h (or 51h53h) ||Sea Green 20 || 0||100|| 50100|| #0F60FF||bgcolor="#00ff8000ffff"||| Bright Cyan || helles Blaugrün || Turquoise vif || Ciano brillante
|-
|20(54h) || 53h ||Bright Cyan 0 || 0||100 0||100 0|| #0FF000||bgcolor="#00ffff000000"||| Black || Schwarz || Noir || Negro
|-
|21(55h) || 5Ah 2 ||Lime 0|| 50 0||100|| 0|| #6F000F||bgcolor="#80ff000000ff"||| Bright Blue || Hellblau || Bleu vif || Azul brillante
|-
|22(56h) || 59h 9 ||Pastel Green 0|| 50||100|| 50 0|| #6F6060||bgcolor="#80ff80008000"||| Green || Grün || Vert || Verde
|-
|23(57h) || 5Bh 11 ||Pastel Cyan 0|| 50||100||100|| #6FF06F||bgcolor="#80ffff0080ff"||| Sky Blue || Himmelblau || Bleu ciel || Azul cielo
|-
|24(58h) || 4Ah 4 ||Bright Yellow ||100||10050|| 0|| 50|| #FF0606||bgcolor="#ffff00800080"||| Magenta || Magenta || Magenta || Magenta
|-
|25(59h) || 22 || 50||100|| 50|| #6F6|| bgcolor="#80ff80" | || Pastel Green || Pastellgrün || Vert pastel || Verde pastel|-| 43h 26 (or 49h5Ah) ||Pastel Yellow 21 || 50||100|| 0|| #6F0|| bgcolor="#80ff00" | || Lime || Limonengrün || Vert citron || Verde lima|-| 27 (5Bh) || 23 || 50||100||100|| #6FF|| bgcolor="#80ffff" | || Pastel Cyan || Pastell-blaugrün|| Turquoise pastel|| Ciano pastel|-| 28 (5Ch) || 3 || 50|| 0|| 0||#FF6600||bgcolor="#ffff80800000"||| Red || Rot || Rouge || Rojo|-| 29 (5Dh) || 5 || 50|| 0||100|| #60F|| bgcolor="#8000ff" | || Mauve || Hellviolett || Mauve || Malva
|-
|2630 (5Eh) || 4Bh 12 || 50|| 50|| 0|| #660|| bgcolor="#808000" | || Yellow || Gelb || Jaune || Amarillo|-| 31 (5Fh) ||Bright White 14 ||10050||10050||100|| #FFF66F||bgcolor="#ffffff8080ff"||| Pastel Blue || Pastellblau || Bleu pastel || Azul pastel
|}
The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).
On an actual Amstrad CPC, the half-intensity colour signal is measured to be closer to 40% rather than the expected 50%. This was verified by [[Grim ]] and independently confirmed by [[Nocash]]. [https://www.grimware.org/doku.php/documentations/devices/gatearray#inkr Source]
* [[CPC Palette]] - some more details
This explains why the Amstrad engineers used these the following values to adapt the old colour palette to the new 12-bit palette on the Amstrad Plus:
* 0% became #0
* 50% became #6. They specifically chose #6 for the 50% value instead of the expected #7 or #8, to better match the real Amstrad CPC palette.
* 100% became #F
They specifically chose #6 for the 50% value instead of #7, to better match the real Amstrad CPC palette.
<br>
=== Green Screen Colours ===
On a green screen (, where all colours are shades of unsaturated green), the firmware colours (in BASIC colours) are in order of increasing intensity. Black is very darkdarkest green, and bright white is bright brightest green, and firmware colour 13 is a medium green. (Thanks to [[Mark Rison|Mark Rison]] for this information)
The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. We have other values. Amstrad preferred to propose a completely different image system, not comparable to a conversion to monochrome, which would have limited the number of brightness levels to 21 (for example, colours 9 and 6 would have had the same luminance).
They opted for a table of 27 linear brightness steps. They assigned values of 1 (1kΩ) for blue, 3 (3.3kΩ) for red, and 9 (10kΩ) for green.
<br> ==== To calculate the luminance value ====
'''Red'''
*0% => do not add anything *50% => add 3 *100% => add 6
'''Green'''
*0% => do not add anything *50% => add 9 *100% => add 18
'''Blue'''
*0% => do not add anything *50% => add 1 *100% => add 2
<br>
== External links ==
*[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]
* [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Gate Array documentation in Amstrad CRTC Compendium]
* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]