Changes

Interrupts on the CPC The CPU maskable interrupts are created generated by the Gate Array based on settings from the CRTC. The Gate Array has an This is done by using a 6bits internal counter R52 (and monitoring the R is for Raster) that counts from 0 to 51, incrementing after each HSYNC signalHSync and VSync signals produced by the CRTC.

On all CRTCsevery falling edge of the HSync signal, R52 interrupts always start 1µs after the end of an HSYNCGate Array will increment the counter by one. But on CRTCs 3/4When the counter reaches 52, HSYNCs occur 1µs later than on CRTCs 0/1/2. Which means that on CRTCs 3/4, interrupts start 1µs later than on CRTCs 0/1/2. This can be adjusted by using the Gate Array raise the INT signal and reset the counter. With 50Hz PAL CRTC register 3settings (one HSync every 64us) this will produce a 300Hz interrupt rate.

R52 will return to 0 and When the CPU acknowledge the Gate Array will send an interrupt request on any of these conditions:* When (eg. it exceeds 51* By setting bit4 of is going to jump to the RMR register of interrupt vector), the Gate Array to 1* At the end will reset bit5 of the 2nd HSYNC after counter, so the start of the VSYNCnext interrupt can't occur closer than 32 HSync.

When the Gate Array sends an interrupt request:*If the interrupts were authorized at the time of the requesta VSync occurs, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction), bit5 of R52 is cleared will wait for two HSync and the interrupt takes place. This happens only '''after the instruction that follows EI''' as this Z80 instruction has a 1-instruction delay.:

Note: On Amstrad Plus, * If the counter>=32 (bit5=1), then no interrupt management system request is seriously beefed upissued and counter is reset to 0. See * If the [[ASIC]] wiki pagecounter<32 (bit5=0), then an interrupt request is issued and counter is reset to 0.

The HSYNC and VSYNC signals are received from falling edge of the HSync trigger the counter, therefore modifying the duration of the HSync with the [[CRTC]]. These signals are then modified Register 3 can delay the interrupt requests by the Gate Array to C-HSYNC and C-VSYNC and merged into a single CSYNC signal that will few microseconds. This can be sent used to the display.adjust interrupt timings between CPC and Plus machines…

When CRTC HSYNC is activeNote: On Amstrad Plus, the Gate Array immediately outputs the palette colour blackinterrupt management system is seriously beefed up. If See the HSYNC is set to 14 characters then black will be output for 14µs[[ASIC]] wiki page.

If a graphics mode change is pending, the HSYNC pulse width needs to be at least 2µs for Gate Array to change the graphics mode=== Timings ===[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)]

C-HSYNC begins 2µs after activation of The INT signal (active low) produced by the CRTC HSYNC and stays Gate Array, is a maximum short pulse of 4µs (1.4us and starts right after the falling edge of the HSync signal is cut short if HSYNC width is greater than 6(produced by the CRTC).

For example, if CRTC R2=46, and CRTC HSYNC width is 14 chars then C-HSYNC starts at 48 and lasts only until 51 included== DI in peace ===[https://acpc.me/ACME/FANZINES Source: Amslive No4 (Madram)]

On Gate Array, even if the duration of the CRTC VSYNC The GA maintains its int request until it is reduced to 2 µseconds, accepted.RST #38 occurs not after the Gate Array will always output black for 26 lines with 4 lines of C-VSYNC to the monitor. While on ASIC/Pre-ASICEI, but after the CRTC VSYNC must be active as long as instruction following the C-VSYNC signal is sent to EI (the monitor. The Gate Array (and ASIC/Pre-ASIC) uses 2 internal counters Z80 needs time to create clean up its CSYNC signal:* H06 counts act). Even if the number of CRTC characters processed during an HSYNC. H06 is incremented int isn't validated by the Gate Array for each CRTC character when CRTC HSYNC is active. The Gate Array activates the C-HSYNC signal when H06 reaches 2Z80, and changes IC (interrupt counter) continues on its graphics mode if a change was pending. It deactivates this signal when H06 reaches 6merry way.* V26 counts But after the number of HSYNCs occuring during EI, a VSYNC. V26 is incremented by test similar to the Gate Array when one seen for the CRTC signals an end of HSYNC. VBL is performed: The Gate Array activates the C-VSYNC signal when V26 reaches 2 (and if VSYNC interrupt is active on ASIC/Pre-ASIC). It deactivates this signal when V26 reaches 6. After the 26th line has been processedgenerated anyway, the Gate Array stops outputting the palette colour black.but:* If CRTC VSYNC is activated again while V26 is still in progressIC < 32, then V26 IC is reset to 0 and starts counting up again unchanged (the HSYNC pulses. The HSYNC signal from the CRTC is 0 when inactive and 1 when active. Same for VSYNC. C-HSYNC and C-VSYNC are composited using the XNOR function. The resulting CSYNC signal next int will then be produced by the Gate Array is 1 when inactive and 0 when active21 to 52 lines later). On a CPC monitor, the CSYNC * Otherwise bit 5 of IC is rendered in "absolute black"set to zero. It is darker than the palette colour black output by the Gate Array. The electron beam is basically turned off. Turning up the brightness level won't make it any brighter. <br>

On a green screen, where all colours are shades of unsaturated green, the firmware colours (in BASIC colours) are in order of increasing intensity. Black is darkest green, bright white is brightest green, and firmware colour 13 is a medium green. The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. We have other values.

The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. Amstrad preferred to propose a completely different image system, not comparable to a conversion to monochrome, which would have limited the number of brightness levels to 21 (for example, colours 9 and 6 would have had the same luminance).