[[File:Amstrad 40007 Gate Array.png|right|thumb|Amstrad 40007 Gate Array]][[File:Amstrad 40010 Gate Array.png|right|thumb|Amstrad 40010 Gate Array]]
== Introduction ==Also designated as Video Gate Array (VGA, not to be confused with the IBM PC compatible graphic card spec).
The gate array is a specially designed chip exclusively for use in the Amstrad CPC and was designed by Amstrad plc.<br>
In the CPC+ system, the functions of the Gate-Array are integrated into a single [[ASIC]]. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate-Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.== Introduction ==
In the [[KC compact]] system, the functions of the The Gate-Array are "emulated" is a specially designed chip exclusively for use in [[TTL logic]] the Amstrad CPC and was designed by the [[Zilog Z8536 CIO]]Amstrad plc.
In the "cost-down" version of the CPC6128CPC+ system, the functions of the Gate-Array are integrated into a single [[ASIC|ASIC]]. When the ASIC is "locked", the extra features are not available and the ASIC operates the same as the Gate Array in the CPC allowing programs written for the CPC to work on the Plus without modification. The ASIC must be "un-locked" to access the new features.
The In the [[KC Compact]] system, the functions of the Gate Array is described here, as it is are "emulated" in a standard CPCTTL chips, [[CIO Overview|CIO]], and its color translation EPROM.
''What does it do?''In the "cost-down" version of the CPC6128, the functions of the Gate Array are integrated into an ASIC.
The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), interrupt generation and memory arrangement.<br>
== Controlling the Gate Array What does it do? ==
The gate array Gate Array is controlled by I/O. The gate array is selected when bit 15 of responsible for the I/O port address is set to "0" display (colour palette, resolution, horizontal and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. Howeververtical sync), to avoid conflict with other devices in the systembus arbitration, these bits should be set to "1"DRAM refresh, interrupt generation and memory arrangement.
The recommended I/O port address is &7Fxx.<br>
The function to be performed is selected by writing data to the Gate-Array, bit 7 and 6 of the data define the function selected (see table below). It is not possible to read from the Gate-Array.== Bus arbitration ==
{|{{Prettytable|widthThe Gate Array arbitrates access to the RAM between the CPU and the video hardware (CRTC and Gate-Array). Every microsecond: 700px; font* The CRTC generates a memory address using it's MA and RA signal outputs. See the [[CRTC]] wiki page to know how the motherboard wiring transforms these signals into the Video Memory Address (VMA).* The Gate Array fetches 2 bytes for each address. /CPU_ADDR is a 1MHz signal. So these 2 bytes are fetched sequentially. They are not interleaved with Z80 access. These bytes are fetched even when the border is on as this is required for DRAM refresh.* The video hardware is given priority so that the display is not disrupted. The Gate-sizeArray generates the "READY" signal which is connected to the "/WAIT" input signal of the CPU. This signal is used to stop the CPU accessing RAM while the video-hardware is accessing it. In fact, the Gate Array allows the Z80 to access the RAM in only 1 out of every 4 cycles. As a result, all instruction timings are stretched so that they are all multiples of a microsecond (1µs), and this gives an effective CPU clock of 3.3Mhz. Unlike the ZX Spectrum or the Amiga, where bus arbitration is restricted to the "contended memory" or "chip RAM", on the CPC it also applies to ROM access and to RAM expansions. So the Z80 always runs at the same speed, regardless of the type of memory being accessed. Last but not least, bus arbitration also applies to I/O access. And memory access is not aligned with I/O access on Z80. Note: 2em;}}On Amstrad Plus, the ASIC also has to handle DMA instruction fetch from RAM.|<br> == DRAM refresh == On Amstrad CPC, the Gate Array is responsible for the DRAM refresh, instead of using the Z80 built-in DRAM refresh mechanism. The reason is that there can only be 3 DRAM accesses per microsecond on this architecture. Doing DRAM refresh on each M1 cycle as it is done on MSX would bog down the CPU speed on CPC given its bus arbitration scheme. The Z80 generates a maximum of one request per microsecond. The CPC also requires two memory accesses per microsecond for reading video data. The CPC specs 4164-20 DRAMs. These require 330nS for a read or write cycle. The CPC also uses the optimised sequential CAS cycles to read the two video data bytes in half a microsecond. [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/the-cpc-revision-zero-article/msg243769/ Source] The way to cause the RAM refresh to fail in both a Plus or normal CPC is simply to stop a few bits of the CRTC address changing (ie. never refresh the selected area). Generally, only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source] <br> == Interrupt generation ==[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)] The CPU maskable interrupts are generated by the Gate Array. This is done by using a 6bits internal counter and monitoring the HSync and VSync signals produced by the CRTC. On every falling edge of the HSync signal, the Gate Array will increment the counter by one. When the counter reaches 52, the Gate Array raise the INT signal and reset the counter. With 50Hz PAL CRTC settings (one HSync every 64us) this will produce a 300Hz interrupt rate. When the CPU acknowledge the interrupt (eg. it is going to jump to the interrupt vector), the Gate Array will reset bit5 of the counter, so the next interrupt can't occur closer than 32 HSync. When a VSync occurs, the Gate Array will wait for two HSync and: * If the counter>=32 (bit5=1), then no interrupt request is issued and counter is reset to 0.* If the counter<32 (bit5=0), then an interrupt request is issued and counter is reset to 0. This 2 HSync delay after a VSync is used to let the main program, executed by the CPU, enough time to sense the VSync (for synchronisation with the display, most likely) before an interrupt service routine is eventually executed. So all the interrupt timings are mostly determined by the CRTC settings. Other than that, the internal interrupt counter can be cleared anytime by software using the Gate Array RMR register. The falling edge of the HSync trigger the counter, therefore modifying the duration of the HSync with the CRTC Register 3 can delay the interrupt requests by a few microseconds. This can be used to adjust interrupt timings between CPC and Plus machines… Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the [[ASIC]] wiki page. === Timings ===[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)] The INT signal (active low) produced by the Gate Array, is a short pulse of 1.4us and starts right after the falling edge of the HSync signal (produced by the CRTC). === DI in peace ===[https://acpc.me/ACME/FANZINES Source: Amslive No4 (Madram)] The GA maintains its int request until it is accepted.RST #38 occurs not after the EI, but after the instruction following the EI (the Z80 needs time to clean up its act). Even if the int isn'Bit 7t validated by the Z80, IC (interrupt counter) continues on its merry way.But after the EI, a test similar to the one seen for the VBL is performed: The interrupt is generated anyway, but:* If IC < 32, IC is unchanged (the next int will then be produced 21 to 52 lines later).* Otherwise bit 5 of IC is set to zero. == Controlling the Gate Array == The gate array is controlled by I/O. The gate array is selected when bit 15 of the I/O port address is set to "0" and bit 14 of the I/O port address is set to "1". The values of the other bits are ignored. However, to avoid conflict with other devices in the system, these bits should be set to "1". The recommended I/O port address is &7Fxx. The Gate Array is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. If you execute an I/O read operation on the Gate Array I/O address, the Gate Array will read an unpredictable value from the databus which will be in high-impedance state. If the value is a valid Gate Array command, it will be executed, otherwise nothing will happen. [https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml Source] The function to be performed is selected by writing data to the Gate Array, the first bits of the data define the function selected (see table below). It is not possible to read from the Gate Array. {|class="wikitable"!colspan=4|''Bit 6''8bit command!rowspan=2|Machine!rowspan=2|''Function'' Register!rowspan=2| Description!rowspan=2| Chip
|-
|! 7! 6! 5! 4..0||0||Select pen
|-
|0||10 || x || style="text-align: center;" | n || All || PENR ||Select colour for selected pena color register || Gate Array
|-
| 0 ||1||0x || style="text-align: center;" | n || All || INKR || Change the value of the currently selected color register ||Select screen mode, rom configuration and interrupt controlGate Array
|-
|1||10 ||Ram Memory Management (note 1)0 || style="text-align: center;" | n || All || RMR || Control Interrupt counter, ROM mapping and Graphics mode || Gate Array
|-
| rowspan="2"|1 || rowspan="2"|0 || rowspan="2"|1 || style="text-align: center;" rowspan="2" | n || All || RMR || ''Ghost register'' || Gate Array (CPC) or locked ASIC (Plus)
|-
| Plus || RMR2 || ASIC & Advanced ROM mapping || Unlocked ASIC
|-
| 1 || 1 ||colspan=2 style="text-align: center;" | n || All || MMR || RAM memory mapping || PAL (only with 128KB or RAM expansion)
|}
===== Note =====The MMR register is not available in the Gate Array, but is performed by a device at the same I/O port address location.
This function is not available in the Gate-Array, but is performed by a device at the same I/O port address location. In the CPC464,CPC664 and KC compact, this function MMR is performed in a an external memory-expansion (e.g. Dk'Tronics 64K Ram RAM Expansion), if this expansion is not present then the function MMR is not available. In the CPC6128, this function is performed by a PAL located on the main PCB, or a memory-expansion. In the 464+ and 6128+ this function is performed by the ASIC or a memory expansion. Please read the document on Ram Management for more information.
==== Pen selection ====In the CPC6128, MMR is performed by a [[PAL16L8|PAL chip]] located on the main PCB, or an external memory expansion.
When bit 7 In the 464+ and bit 6 are set to "0"6128+, MMR is performed by the remaining bits determine which pen is to have its colour changedASIC or an external memory expansion. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", Please read the value contained in bits 3-0 is ignored and the border is selecteddocument on RAM management for more information.
The pen remains selected until another is chosen.<br>
Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens.== Registers ==
===== Note: The Plus palette capabilities are only accessible through the [[Default I/O Port Summary =====|ASIC I/O page]]. Registers PENR and INKR are not needed in that case.
=== Register PENR (Select a color register) ===
{|{{Prettytable|width: 700px; fontWhen bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-size: 2em;}}0 is ignored and the border is selected. The pen remains selected until another is chosen. Each mode has a fixed number of pens. Mode 0 has 16 pens, mode 1 has 4 pens and mode 2 has 2 pens. ==== Summary ==== {|''class="wikitable"!Bit''||''!Value''||''!Function''
|-
|7||0||rowspan="2" |Gate Array function "Pen Selection"PENR register
|-
|6||0
|-
|5||-||not used
|-
|4||1||Select border
|-
|3||x||rowspan="4" |Ignored
|-
|2||x
|-
|1||x|-|0||x
|-
| 0 || x
|}
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|''!Bit''||''!Value''||''!Function''
|-
|7||0||rowspan="2" |Gate Array function "Pen Selection"PENR register
|-
|6||0
|-
|5||-||not used
|-
|4||10 ||Select pen
|-
|3||x||rowspan="4" |Pen number
|-
|2||x
|-
|1||x|-|0||x
|-
| 0 || x
|}
==== Colour selection ====<br>
Once === Register INKR (Change the pen has been value of the currently selected the colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.color register) ===
Even though there is provision for 32 colours, only 27 are possibleOnce the pen has been selected its colour can then be changed. The remaining colours are duplicates of those already in Bits 4 to 0 specify the hardware colour number from the hardware colour palette.
===== Summary =====Even though there is provision for 32 colours, only 27 are possible. The remaining colours are duplicates of those already in the colour palette.
==== Summary ==== {|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|''!Bit''||''!Value''||''!Function''
|-
|7||0||rowspan="2" |Gate Array function "Colour selection"INKR register
|-
|6||1
|-
|5||-||not used
|-
|4||x||rowspan="5" |Colour number x
|-
|3||x
|-
|2||x
|-
|1||x|-|0||x
|-
| 0 || x
|}
==== Hardware colour palette ====<br>
{=== Register RMR (Control Interrupt counter, ROM mapping and Graphics mode) === This is a general purpose register responsible for the [[Video modes|graphics mode]] and the ROM configuration. ==== Graphics mode selection ==== The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below. {{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|''Colour Number''||''Colour Name''||''Color''!Bit 1!Bit 0!Screen mode
|-
|0||White0 ||bgcolor="#808080"|Mode 0, 160x200 resolution, 16 colours
|-
|10 ||White (note 1)||bgcolor="#808080"|Mode 1, 320x200 resolution, 4 colours
|-
|21 ||Sea Green0 ||bgcolor="#00FF80"|Mode 2, 640x200 resolution, 2 colours
|-
|31 ||Pastel Yellow1 ||bgcolorMode 3, 160x200 resolution, 4 colours (undocumented)|} * Mode 3 is not official. From the combinations possible, we can see that 4 modes can be defined, although the Amstrad only has 3. Mode 3 is similar to mode 0, because it has the same resolution, but it is limited to only 4 colours. Mode 3 is not supported by the [[KC Compact]] (which outputs black in Mode 3). Mode changing is synchronised with HSYNC. If the mode is changed, it will take effect from the next HSYNC. ==== ROM configuration selection ==== Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &0000-&3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &0000-&3FFF will return data in the ROM. When a value is written to &0000-&3FFF, it will be written to the RAM underneath the ROM. When it is disabled, data read from &0000-&3FFF will return the data in the RAM. Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &C000-&FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &c000-&ffff, will return data in the ROM. When data is written to &c000-&FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &c000-&ffff it will be the data in the RAM. Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information. ==== Summary ==== {| class="#FFFF50wikitable"|!Bit!Value!Function
|-
|47 ||Blue1 ||bgcolorrowspan="#0000802"|Gate Array RMR register
|-
|56 ||Purple||bgcolor="#FF0080"|0
|-
|65 ||Cyan- ||bgcolor="#008080"|''must be 0 on Plus machines with ASIC unlocked''
|-
|74 ||Pinkx ||bgcolor="#FF8080"|Interrupt generation control
|-
|83 ||Purple (note 1)x ||bgcolor1="#FF0080"|Upper ROM area disable, 0=Upper ROM area enable
|-
|92 ||Pastel Yellow (note 1)x ||bgcolor1="#FFFF50"|Lower ROM area disable, 0=Lower ROM area enable
|-
|101 ||Bright Yellowx ||bgcolorrowspan="#FFFF802"|Graphics Mode selection
|-
|110 ||Bright Whitex|} <br> === Register RMR2 (ASIC & Advanced ROM mapping) === This register exists only in Plus or GX4000, and is only accessible when the ASIC is unlocked. {|bgcolorclass="#FFFFFFwikitable"|!Bit!Value!Function
|-
|127 ||Bright Red1 ||bgcolorrowspan="#FF00003"|Gate Array RMR2 register
|-
|136 ||Bright Magenta||bgcolor="#FF00FF"|0
|-
|145 ||Orange||bgcolor="#FF8000"|1
|-
|154 ||Pastel Magentax ||bgcolorrowspan="#FF80FF2"|RMR addressing mode
|-
|163 ||Blue (note 1)||bgcolor="#000080"|x
|-
|172 ||Sea Green (note 1)x ||bgcolorrowspan="#00FF803"|Physical ROM number (0..7)
|-
|181 ||Bright Green||bgcolor="#00FF00"|x
|-
|190 ||Bright Cyanx|} {|bgcolorclass="#00FFFFwikitable"|+ RMR addressing modes!Bit 4!Bit 3!Lower ROM![[ASIC|ASIC I/O page]]
|-
|200|0|Black||bgcolor="#000000"&0000-&3FFF|Disabled
|-
|210|1|Bright Blue||bgcolor="#0000FF"&4000-&7FFF|Disabled
|-
|221|0|Green||bgcolor="#008000"&8000-&BFFF|Disabled
|-
|231|1|Sky Blue&0000-&3FFF|&4000-&7FFF|bgcolor} The physical ROMs are also accessible as upper ROMs by using the [[Upper ROM Bank Number]] port and the RMR register. <br> === Register MMR (RAM memory mapping) ==="#0080FF"| This register exists only in CPCs with 128K RAM (like the CPC 6128), or CPCs equipped with [[Standard Memory Expansions]]. Note: In the CPC 6128, the register is a separate [[PAL16L8|-PAL chip]] that assists the Gate Array chip. {|24||Magenta||bgcolorclass="#800080wikitable"|!Bit!Value!Function
|-
|257 ||Pastel Green1 ||bgcolorrowspan="#80FF802"|Gate Array MMR register
|-
|266 ||Lime||bgcolor="#80FF00"|1
|-
|275 ||Pastel Cyanx ||bgcolorrowspan="#80FFFF3"|64K bank number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]]
|-
|284 ||Red||bgcolor="#800000"|x
|-
|293 ||Mauve||bgcolor="#8000FF"|x
|-
|302 ||Yellowx ||bgcolorrowspan="#8080003"|RAM Config (0..7)
|-
|311 ||Pastel Blue||bgcolor="#8080FF"|x
|-
| 0 || x
|}
===== Notes =====
This The 3bit RAM Config value is not an official colour used to access the second 64K of the total 128K RAM that is built into the CPC 6128 or the additional 64K-512K of standard memory expansions. These contain up to eight 64K ram banks, which are selected with bit 3-5. A standard CPC 6128 only contains bank 0. Normally the register is set to 0, so that only the first 64K RAM are used (identical to the CPC 464 and 664 models). The register can be used to select between the following eight predefined configurations only:
Select screen mode and rom configuration -Address- 0 1 2 3 4 5 6 7 0000-3FFF RAM_0 RAM_0 '''RAM_4''' RAM_0 RAM_0 RAM_0 RAM_0 RAM_0 4000-7FFF RAM_1 RAM_1 '''RAM_5''' '''RAM_3''' '''RAM_4''' '''RAM_5''' '''RAM_6''' '''RAM_7''' 8000-BFFF RAM_2 RAM_2 '''RAM_6''' RAM_2 RAM_2 RAM_2 RAM_2 RAM_2 C000-FFFF RAM_3 '''RAM_7''' '''RAM_7''' '''RAM_7''' RAM_3 RAM_3 RAM_3 RAM_3
This The Video RAM is a general purpose register responsible for always located in the screen mode and the rom configurationfirst 64K, VRAM is in no way affected by this register.
==== Screen mode selection ====<br>
The function of bits 1 and 0 is to define == Programming the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.Gate Array - Examples ==
{|{{Prettytable|width: 700px; font-size: 2em;}}|''Bit 1''||''Bit Defining the colours, <br>Setting pen 0''||''Screen mode'' to Bright White. |-|0||0||Mode 0<pre>LD BC, 160x200 resolution, 16 colours7F00 ;Gate Array port|-|0||1||Mode 1LD A, 320x200 resolution, 4 colours|-|1||%00000000+0||Mode 2 ;Pen number (and Gate Array function)OUT (C), 640x200 resolution, 2 coloursA ;Send pen number|-|1||1||Mode 3, 160x200 resolutionLD A, 4 colours %01000000+11 ;Pen colour (note 1and Gate Array function)|-OUT (C),A ;Send it|}RET
This Setting the mode is not official. From the combinations possibleand ROM configuration, we can see that 4 modes can be defined, although the Amstrad only has 3. Mode 3 is similar to mode 0, because it has the same resolution2, but it is limited to only 4 coloursupper and lower ROM disabled.
LD BC,7F00 ;Gate array portLD A,%10000000+%00001110 ;Mode changing is synchronised with HSYNC. If the mode is changedand ROM selection (and Gate Array function)OUT (C), A ;Send it will take effect from the next HSYNC.RET</pre>
==== Rom configuration selection =Misc ===
Bit 2 The hardware colour number is used different to enable or disable the lower rom area. The lower rom area occupies memory addressess &0000-&3fff and is colour range used to access by the operating system rom. When the lower rom area is is enabledfirmware, reading from &0000-&3FFF will return data in the rom. When so a value conversion chart is written to &0000-&3FFF, it will be written to provided for the ram underneath the rom. When it is disabled, data read from &0000-&3FFF will return the data in corresponding firmware/hardware colour values and the ramcorresponding colour name.
Similarly, bit 3 controls enabling or disabling of the upper rom area. The upper rom area occupies memory addressess &C000-&FFFF and is BASIC or any expansion roms which may be plugged into a rom board/box. See the document on upper rom selection for more details. When the upper rom area enabled, reading from &c000-&ffff, will return data in the rom. When data is written to &c000-&FFFF, it will be written to the ram at the same address as the rom. When the upper rom area is disabled, and data is read from &c000-&ffff the data returned will be the data in the ram.=== Note ===
Bit 4 controls The firmware keeps track of the interrupt generationcolours it is using. It can be used to delay Every VSYNC (assuming interruptsare enabled) the firmware sets the colours. See This enables the user to have flashing colours. If the user selects a new colour using the gate array, the new colour will flash temporarily and then return to its original colour. This is due to the firmware resetting the colour. When using the firmware, use its routines to select the colour, and the document on interrupt generation for more informationcolour will remain.
===== Summary =====Example: [For whatever reason, this example does NOT refer to the above firmware stuff]<pre>ld bc,7f00+1 ;Gate array function (set pen);and pen numberout (c),cld bc,7f00 ;41 ;Gate array function (set colour);and colour numberout (c),cret</pre>
{|{{Prettytable|width: 700px; font-size: 2em;}}<br>|''Bit''||''Value''||''Function'' == Video memory structure == {|-class="wikitable"|7||0||!rowspan=2|Gate Array function Graphics Mode!colspan=8|-VRAM byte!colspan=8|6||1Displayed Pixels!rowspan=2|-Definition!rowspan=2|5||-||not usedPixel clock!rowspan=2|-|4||x||Interrupt generation controlDefault resolution
|-
|!7!6!5!4!3||x||*!2!1 Upper rom area disable*!0 Upper rom area enable!1!2!3!4!5!6!7!8
|-
|20|A0|xB0|A2|B2*1 Lower rom area disable|A1*0 Lower rom area enable|B1|A3|B3|colspan=4 style="text-align: center;"|A|colspan=4 style="text-align: center;"|B|2 pixels in 16 colours|4 MHz|160x200, 20-column text
|-
|1|A0|xB0|C0|rowspanD0|A1|B1|C1|D1|colspan=2style="text-align: center;"|A|colspan=2 style="text-align: center;"|B|colspan=2 style="text-align: center;"|C|colspan=2 style="text-align: center;"|D|4 pixels in 4 colours|8 MHz|Mode slection320x200, 40-column text
|-
|02|A0|xB0|C0|D0|E0|F0|G0|H0|A|B|C|D|E|F|G|H|8 pixels in 2 colours|16 MHz|640x200, 80-column text
|-
|3
|A0
|B0
|x
|x
|A1
|B1
|x
|x
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 4 colours
|4 MHz
|160x200, 20-column text
|}
== Programming the Gate Array - Examples ==<br>
Defining the colours, <br>Setting pen 0 to Bright White.== Split rasters ==
<pre>LD BCOn the CPC,7F00 ;Gate Array portLD A,%00000000+0 ;Pen number split rasters occur halfway (and Gate Array functionafter the 8th mode2 pixel)OUT (C),A ;Send pen numberLD A,%01000000+11 ;Pen colour (and Gate Array function)OUT (C),A ;Send itRETthrough the rendering of a CRTC character.
Setting the mode and rom configurationOn Amstrad Plus, Mode 2, upper and lower rom disabledsplit rasters occur quarter of the way (after the 4th mode2 pixel) through the rendering of a CRTC character.
LD BCTo easily make split rasters compatible with both the CPC and the Plus machines,7F00 ;Gate array portLD A,%10000000+%00001110 ;Mode and rom selection one can use the ASIC soft-scroll control register (and Gate Array functionSSCR)OUT (C),A ;Send itRET</pre>to finely adjust the horizontal position of the graphics.
<br> ==Palette R,G,B definitions == Conversion chart ==== There are 27 colours which are generated from red, green and blue mixed in different quantities. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-colour. To display a CPC image you will need to use a analogue monitor with a composite sync.
The hardware colour number is different to the colour range used by the firmware, so a conversion chart is provided for the corresponding firmware/hardware colour values and the corresponding colour name.<br>
===== Note ==Palette sorted by Firmware Colour Numbers ===
The firmware keeps track of the colours it is using. Every VSYNC (assuming interrupts are enabled) the firmware sets the colours. This enables the user to have flashing colours. If the user selects a new colour using the gate array, the new colour will flash temporarily and then return to it's original colour. This palette is due to the firmware re- setting the colour. When using the firmware, use it's routines to select the colour, and the colour will remainsorted by luminance value.
{|{{Prettytable|width: 700px; font-size: 2em;}}|''Firmware Colour Number''||''Colour Name''||''Hardware Number''||''Quick reference colour value''||''Color''class="wikitable"
|-
|0||Black||20||&54||bgcolor="#000000"|
|-
|1||Blue||4||&44||bgcolor="#000080"|!Firmware Number!Hardware Number!Colour Name!R %!G %!B %!ASIC!Colour
|-
|20||Bright Blue54h ||21Black ||&55 0|| 0|| 0|| #000||bgcolor="#0000FF000000"|
|-
|31||Red44h (or 50h) ||28Blue ||&5C 0|| 0|| 50|| #006||bgcolor="#800000000080"|
|-
|42||Magenta55h ||24Bright Blue ||&58 0|| 0||100|| #00F||bgcolor="#8000800000ff"|
|-
|53||Mauve5Ch || 29Red ||&5D50|| 0|| 0|| #600||bgcolor="#8000FF800000"|
|-
|64||Bright Red58h ||12Magenta ||&4C50|| 0|| 50|| #606||bgcolor="#FF0000800080"|
|-
|75||Purple5Dh || 5Mauve ||&4550|| 0||100|| #60F||bgcolor="#FF00808000ff"|
|-
|86|| 4Ch ||Bright MagentaRed ||13100||&4D 0|| 0|| #F00||bgcolor="#FF00FFff0000"|
|-
|97||Green45h (or 48h) ||22Purple ||&56100|| 0|| 50|| #F06||bgcolor="#008000ff0080"|
|-
|108||Cyan4Dh ||6Bright Magenta ||&46100|| 0||100|| #F0F||bgcolor="#008080ff00ff"|
|-
|119||Sky Blue56h ||23Green ||&57 0|| 50|| 0|| #060||bgcolor="#0080FF008000"|
|-
|1210||Yellow46h ||30Cyan ||&5E 0|| 50|| 50|| #066||bgcolor="#808000008080"|
|-
|1311||White57h ||Sky Blue || 0||&4050||100|| #06F||bgcolor="#8080800080ff"|
|-
|1412||Pastel Blue5Eh ||31Yellow ||&5F50|| 50|| 0|| #660||bgcolor="#8080FF808000"|
|-
|1513||Orange40h (or 41h) ||14White ||&4E50|| 50|| 50||#666||bgcolor="#FF8000808080"|
|-
|1614||Pink5Fh ||7Pastel Blue ||&4750|| 50||100|| #66F||bgcolor="#FF80808080ff"|
|-
|1715||Pastel Magenta4Eh ||15Orange ||&4F100|| 50|| 0|| #F60||bgcolor="#FF80FFff8000"|
|-
|1816||Bright Green47h ||18Pink ||&52100|| 50|| 50|| #F66||bgcolor="#00FF00ff8080"|
|-
|1917||Sea Green4Fh ||2Pastel Magenta ||&42bgcolor100|| 50||100|| #F6F||bgcolor="#00FF80ff80ff"|
|-
|2018|| 52h ||Bright CyanGreen ||19 0||&53100|| 0|| #0F0||bgcolor="#00FFFF00ff00"|
|-
|2119||Lime42h (or 51h) ||26Sea Green ||&5A 0||100|| 50|| #0F6||bgcolor="#80FF0000ff80"|
|-
|2220||Pastel Green53h ||25Bright Cyan ||&59 0||100||100|| #0FF||bgcolor="#80FF8000ffff"|
|-
|2321||Pastel Cyan5Ah ||27Lime ||&5B50||100|| 0|| #6F0||bgcolor="#80FFFF80ff00"|
|-
|2422||Bright Yellow59h ||10Pastel Green ||&4A50||100|| 50|| #6F6||bgcolor="#FFFF8080ff80"|
|-
|2523|| 5Bh ||Pastel YellowCyan ||350||&43100||100|| #6FF||bgcolor="#FFFF8080ffff"|
|-
|2624|| 4Ah ||Bright WhiteYellow ||11100||&4B100|| 0|| #FF0||bgcolor="#FFFFFFffff00"|
|-
|25|| 43h (or 49h) ||Pastel Yellow ||100||100|| 50||#FF6||bgcolor="#ffff80"|
|-
|26|| 4Bh ||Bright White ||100||100||100|| #FFF||bgcolor="#ffffff"|
|}
This chart also gives a quick reference guide for programming Note: We can observe that the official Amstrad names of some colours. The number are a bit silly: "red" is the colour number which can be sent directlyin fact brown, once the pen has been selected, to get the colour wanted"yellow" is in fact khaki and "white" is in fact grey.
Example:<br>
<pre>ld bc,7f00+1 ;Gate array function (set pen);and pen numberout (c),cld bc,7f00 ;41 ;Gate array function (set colour);and colour numberout (c),cret</pre>=== Amstrad Colour Names ===
==== Pallette R,G,B definitions ====<gallery> There are 27 colours which are generated from red, green and blue mixed in different quantitiesCpc 6128 master colour chat. There are 3 levels of red, 3 levels of green and 3 levels of blue, and these can be thought of as off/no colour, half-on/half-colour, and on/full-jpg|Master colourchartCpc 6128 farbtabelle.jpg|FarbtabelleCpc 6128 palette des couleurs.jpg|Palette des couleursTo display a CPC image you will need to use a analogue monitor with a composite syncCpc 6128 tabla de colores.jpg|Tabla de colores</gallery>
This table shows the relationship between hardware colour number, colour name and RGB mixing.<br>
=== Palette sorted by Hardware Colour Numbers ===
{|{{Prettytable|width: 700px; font-size: 2em;}}|''Hardware Colour Index''||''Colour Name''||''R %''||''G %''||''B %''||''Color'' class="wikitable"
|-
|0||White||align="right"|50||align="right"|50||align="right"|50||bgcolor="#808080"|!Hardware Number!Firmware Number!R %!G %!B %!ASIC!Colour!Colour Name!German Name!French Name!Spanish Name
|-
|1 0 (40h) ||White13 ||align="right"50||50||align="right"|50||align="right"|50#666||bgcolor="#808080"||| White || Weiß || Blanc || Blanco
|-
|2 1 (41h) ||Sea Green(13) ||align="right"50|0|50|align="right"|10050||align="right"|50#666||bgcolor="#00FF80808080"||| White || Weiß || Blanc || Blanco
|-
|3 2 (42h) ||Pastel Yellow19 ||align="right" 0||100||align="right"50|100|#0F6|align| bgcolor="right#00ff80"|50||bgcolor="#FFFF80"Sea Green || Seegrün || Vert marin ||Verde marino
|-
|4 3 (43h) ||Blue25 ||align="right"100|0|100|align="right"|050||align="right"|50#FF6||bgcolor="#000080ffff80"||| Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
|5 4 (44h) ||Purple1 ||align="right" 0|100||align="right"| 0||align="right"|50|| #006||bgcolor="#FF0080000080"||| Blue || Blau || Bleu || Azul
|-
|6 5 (45h) ||Cyan7 ||align="right"100|| 0||align="right"|50||align="right"|50#F06||bgcolor="#008080ff0080"||| Purple || Purpur || Pourpre || Púrpura
|-
|7 6 (46h) ||Pink10 ||align="right" 0|100|50|align="right"|50||align="right"|50#066||bgcolor="#FF8080008080"||| Cyan || Blaugrün || Turquoise || Ciano
|-
|8 7 (47h) ||Purple16 ||align="right"|100||align="right"50|0|50|align="right"|50#F66||bgcolor="#FF0080ff8080"||| Pink || Rosa || Rose || Rosa
|-
|9 8 (48h) ||Pastel Yellow(7) ||align="right"|100||align="right" 0|100|50|align="right"|50#F06||bgcolor="#FFFF80ff0080"||| Purple || Purpur || Pourpre || Púrpura
|-
|10 9 (49h) ||Bright Yellow(25) ||align="right"|100||align="right"|100||align="right"50|0| #FF6||bgcolor="#FFFF00ffff80"||| Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
|1110 (4Ah) ||Bright White24 ||align="right"|100||align="right"|100||align="right" 0|100| #FF0||bgcolor="#FFFFFFffff00"||| Bright Yellow || Hellgelb || Jaune vif || Amarillo brillante
|-
|1211 (4Bh) ||Bright Red26 ||align="right"|100||align="right"100|0|100|align="right"|0#FFF||bgcolor="#FF0000ffffff"||| Bright White || Leuchtendweiß || Blanc brillant || Blanco brillante
|-
|1312 (4Ch) ||Bright Magenta6 ||align="right"|100||align="right" 0|| 0||align="right"|100#F00||bgcolor="#FF00FFff0000"||| Bright Red || Hellrot || Rouge vif || Rojo brillante
|-
|1413 (4Dh) ||Orange8 ||align="right"|100||align="right" 0|50|100|align="right"|0#F0F||bgcolor="#FF8000ff00ff"||| Bright Magenta|| helles Magenta || Magenta vif || Magenta brillante
|-
|1514 (4Eh) ||Pastel Magenta15 ||align="right"|100||align="right"|50||align="right" 0|100| #F60||bgcolor="#FF80FFff8000"||| Orange || Orange || Orange || Naranja
|-
|1615 (4Fh) ||Blue17 ||align="right"100|0|50|align="right"|0100||align="right"|50#F6F||bgcolor="#000080ff80ff"||| Pastel Magenta|| Pastell-magenta || Magenta pastel || Magenta pastel
|-
|1716 (50h) ||Sea Green(1) ||align="right"| 0||align="right" 0|100|50|align="right"|50#006||bgcolor="#00FF80000080"||| Blue || Blau || Bleu || Azul
|-
|1817 (51h) ||Bright Green(19) ||align="right"| 0||align="right"|100||align="right"50|0| #0F6||bgcolor="#00FF0000ff80"||| Sea Green || Seegrün || Vert marin || Verde marino
|-
|1918 (52h) ||Bright Cyan18 ||align="right"| 0||align="right"|100||align="right" 0|100| #0F0||bgcolor="#00FFFF00ff00"||| Bright Green || Hellgrün || Vert vif || Verde brillante
|-
|2019 (53h) ||Black20 ||align="right"| 0||align="right"100|0|100|align="right"|0#0FF||bgcolor="#00000000ffff"||| Bright Cyan || helles Blaugrün || Turquoise vif || Ciano brillante
|-
|2120 (54h) ||Bright Blue0 ||align="right"| 0||align="right"| 0||align="right" 0|100| #000||bgcolor="#0000FF000000"||| Black || Schwarz || Noir || Negro
|-
|2221 (55h) ||Green2 ||align="right"| 0||align="right" 0|50|100|align="right"|0#00F||bgcolor="#0080000000ff"||| Bright Blue || Hellblau || Bleu vif || Azul brillante
|-
|2322 (56h) ||Sky Blue9 ||align="right"| 0||align="right"|50||align="right" 0|100| #060||bgcolor="#0080FF008000"||| Green || Grün || Vert || Verde
|-
|2423 (57h) ||Magenta11 ||align="right" 0||50||align="right"100|0|#06F|align| bgcolor="right#0080ff"|50||bgcolor="#800080"Sky Blue || Himmelblau || Bleu ciel ||Azul cielo
|-
|2524 (58h) ||Pastel Green4 ||align="right"|50||align="right" 0|100|50|align="right"|50#606||bgcolor="#80FF80800080"||| Magenta || Magenta || Magenta || Magenta
|-
|2625 (59h) ||Lime22 ||align="right"|50||align="right"|100||align="right"50|0| #6F6||bgcolor="#80FF0080ff80"||| Pastel Green || Pastellgrün || Vert pastel || Verde pastel
|-
|2726 (5Ah) ||Pastel Cyan21 ||align="right"|50||align="right"|100||align="right" 0|100| #6F0||bgcolor="#80FFFF80ff00"||| Lime || Limonengrün || Vert citron || Verde lima
|-
|2827 (5Bh) ||Red23 ||align="right"|50||align="right"100|0|100|align="right"|0#6FF||bgcolor="#80000080ffff"||| Pastel Cyan || Pastell-blaugrün|| Turquoise pastel|| Ciano pastel
|-
|2928 (5Ch) ||Mauve3 ||align="right"|50||align="right"| 0||align="right" 0|100| #600||bgcolor="#8000FF800000"||| Red || Rot || Rouge || Rojo
|-
|3029 (5Dh) ||Yellow5 ||align="right"|50||align="right" 0|50|100|align="right"|0#60F||bgcolor="#8080008000ff"||| Mauve || Hellviolett || Mauve || Malva
|-
|3130 (5Eh) ||Pastel Blue12 ||align="right"|50||align="right"|50||align="right" 0|100| #660||bgcolor="#8080FF808000"||| Yellow || Gelb || Jaune || Amarillo
|-
| 31 (5Fh) || 14 || 50|| 50||100|| #66F|| bgcolor="#8080ff" | || Pastel Blue || Pastellblau || Bleu pastel || Azul pastel
|}
==== RGB assignments for the software colours ====<br>
This is simply a sidenote to illustrate a pattern in the RGB assignments of the software colours and to show how their value is calculated.=== Intensities ===
{|{{Prettytable|width: 700px; fontThe 0%, 50%, and 100% values in the above tables are "should-size: 2em;}}|''Firmware Colour Number''||''Colour Name''||'be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R %''||'',G %''||'',B %''||''Color''tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).|-|0||Black||0||0||0||bgcolor="#000000"| |On an actual Amstrad CPC, the half-|1||Blue||0||0||intensity colour signal is measured to be closer to 40% rather than the expected 50||bgcolor="%. This was verified by [[Grim]] and independently confirmed by [[Nocash]]. [https://www.grimware.org/doku.php/documentations/devices/gatearray#000080"| inkr Source]|* [[CPC Palette]] -some more details|2||Bright Blue||0||0||100||bgcolor="#0000FF"||This explains why the Amstrad engineers used the following values to adapt the old colour palette to the new 12-bit palette on the Amstrad Plus:|3||Red||50||* 0||0||bgcolor="% became #800000"||-|4||Magenta||50||0||50||bgcolor="#800080"||-|5||Mauve||* 50||0||100||bgcolor="% became #8000FF"||-|6||Bright Red||100||0||0||bgcolor=". They specifically chose #FF0000"||-|7||Purple||100||0||6 for the 50||bgcolor="% value instead of the expected #FF0080"|7 or #8, to better match the real Amstrad CPC palette.|-|8||Bright Magenta||* 100||0||100||bgcolor="% became #FF00FF"|F|-|9||Green||0||50||0||bgcolor="#008000"|<br>|-|10||Cyan||0||50||50||bgcolor="#008080"||-|11||Sky Blue||0||50||100||bgcolor="#0080FF"||-|12||Yellow||50||50||0||bgcolor="#808000"|Green Screen Colours ===|-|On a green screen, where all colours are shades of unsaturated green, the firmware colours are in order of increasing intensity. Black is darkest green, bright white is brightest green, and firmware colour 13||White||50||50||50||bgcolor="#808080"|is a medium green.|-|14||Pastel Blue||50||50||100||bgcolor="#8080FF"|The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. Amstrad preferred to propose a completely different image system, not comparable to a conversion to monochrome, which would have limited the number of brightness levels to 21 (for example, colours 9 and 6 would have had the same luminance).|-|15||Orange||100||50||0||bgcolor="#FF8000"|They opted for a table of 27 linear brightness steps. They assigned values of 1 (1kΩ) for blue, 3 (3.3kΩ) for red, and 9 (10kΩ) for green.|-|16||Pink||100||50||50||bgcolor="#FF8080"||-|17||Pastel Magenta||100||50||100||bgcolor="#FF80FF"||-|18||Bright Green||0||100||0||bgcolor="#00FF00"|= To calculate the luminance value ====|-|19||Sea Green||0||100||50||bgcolor="#00FF80"|'''Red''' |-|20||Bright Cyan||*0||100||100||bgcolor% ="#00FFFF"|> do not add anything |-|21||Lime||*50||100||0||bgcolor% ="#80FF00"|> add 3 |-|22||Pastel Green||50||*100||50||bgcolor% ="#80FF80"|> add 6 |-|23||Pastel Cyan||50||100||100||bgcolor="#80FFFF"|'''Green''' |-|24||Bright Yellow||100||100||*0||bgcolor% ="#FFFF00"|> do not add anything |-|25||Pastel Yellow||100||100||*50||bgcolor% ="#FFFF80"||-> add 9 |26||Bright White||*100||100||100||bgcolor% ="#FFFFFF"||-|}> add 18
===== To calculate the colour value ===== '''Blue'''
'''Red'''*0% => do not add anything *50% => add 1 *100% => add 2
0% => do not add anything <br>
50% => add 3= Pictures ==
100% => add 6<gallery>Image:40010_am2_metal.jpg|40010 GA Metal LayerImage:40010_am2_acid.jpg|40010 GA with Metal Layer removedImage:40226_am4_metal.jpg|40226 PreASIC Metal Layer</gallery>
'''Green'''[[File:Ga.pinout.40007.png]] [[File:Ga.pinout.40008.40010.png]]
0% => do not add anythingNote: Some CPC motherboards can accommodate both types of Gate Array pinouts. [https://thecheshirec.at/2024/10/06/il-existe-une-carte-multi-gate-array-et-cest-amstrad-qui-la-faite/ Source]
50% => add 9<br>
100% => add 18= External links ==*[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]* [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Gate Array documentation in Amstrad CRTC Compendium]* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]
'''Blue'''<br>
0% => do not add anything=See also==
50% => add 1*[[Gate Array and ASIC Pin-Outs]]*[[PAL16L8]] : for RAM arrangement*[[ASIC]] : for Plus users
100% => add 2*[[CRTC]] : the other video stuff*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.
Green Screen Colours*[[Video modes]] : for other informations on colours and pixels.
On a green screen (where all colours are shades of green), the colours (in the software/firmware colours), are in order of increasing intensity. So that black is very dark, and white is bright green, and colour 13 is a medium green. (Thanks to *[[Mark RisonMedia:40010-simplified V03.pdf]] for this information)[https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Forum thread] Gate Array schematics - reverse engineered by Gerald
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