Revision as of 09:28, 2 February 2025

The Motorola 68000 (commonly abbreviated as 68k) is a landmark microprocessor introduced in 1979 by Motorola Semiconductor.

It is frequently characterized as a “16/32‑bit” processor as its design exhibits a unique hybrid architecture: the programming model is 32‑bit (with 32‑bit registers and a 32‑bit instruction set), yet its data arithmetic is carried out by a 16‑bit arithmetic logic unit (ALU) and it utilizes a 16‑bit external data bus. Its 24‑bit address bus enables direct access to 16 megabytes of memory, a very large space for the era.

This innovative compromise helped lower chip pin count and cost while delivering performance that spurred a generation of computing systems.

Although there were definitely other CPUs in use in the 1980s, the vast majority of microcomputers people had at home or at the office used either a MOS 6502 (or one of its variants), a Zilog Z80, an early member of the Intel 8086 family, or a Motorola 68000.

History

Motorola developed the 68000 in the late 1970s to compete with emerging 16‑bit designs and to counter the limitations of 8‑bit microprocessors like the Motorola 6800.

In designing the 68000, Motorola’s team (led by figures such as Tom Gunter) adopted a strategy of using a 32‑bit instruction set with a 16‑bit ALU to balance performance with production cost and complexity. The result was a processor that offered a large, flat address space without segmentation and supported a rich set of operations—qualities that made it suitable for both desktop systems and embedded applications.

The success of the 68000 spurred a family of processors (68010, 68020, 68030, 68040, 68060) that gradually incorporated full 32‑bit ALUs, on‑chip caches, and integrated MMUs and FPUs. Despite these advances, the original 68000 remained widely used for many years, with its derivatives still found in embedded systems even after desktop computing shifted toward RISC and x86 architectures.

Motorola used even numbers for major revisions to the CPU core such as 68000, 68020, 68040 and 68060. The 68010 was a revised version of the 68000 with minor modifications to the core, and likewise the 68030 was a revised 68020 with some more powerful features, none of them significant enough to classify as a major upgrade to the core. The 68050 was reportedly "a minor upgrade of the 68040" that lost a battle for resources within Motorola. They considered the 68050 as not meriting the necessary investment in production of the part.

Applications

The Motorola 68000’s combination of a robust 32‑bit programming model and efficient 16‑bit data processing made it a versatile CPU that was deployed in numerous systems:

• Personal Computers and Workstations: Early Macintosh models, the Amiga, the Atari ST, and various Unix workstations leveraged the 68000 for its powerful instruction set and efficient memory addressing. The Sinclair QL used the nearly identical 68008 (which featured an 8‑bit external data bus for cost savings).
• Video Game Consoles: Systems such as the Sega Genesis (Mega Drive) and arcade platforms utilized the 68000 to deliver high performance in graphics and sound processing.
• Embedded Systems: The processor’s cost‑effectiveness and robust design made it popular for industrial controllers, laser printers, and other embedded devices. Even decades later, derivatives of the 68000 architecture (such as ColdFire and DragonBall) continue to be used in specialized applications.

Architecture

Microcode

Whereas the Z80 and the 6502 CPUs use an hardwired control unit, the 68000 uses microcode instead.

To execute a machine instruction, the computer internally executes several simpler micro-instructions, specified by the microcode. In other words, microcode forms another layer between the machine instructions and the hardware.

The actual internal representation is a combination of "microcode" and "nanocode". The 68000 has 544 17-bit microcode words which dispaches to 366 68-bit nanocode words. Source

The microcode is a series of pointers into assorted microsubroutines in the nanocode. The nanocode performs the actual routing and selecting of registers and functions, and directs results. Decoding of an instruction's op code generates starting addresses in the microcode for the type of operation and the addressing mode. Source

Hybrid 16/32‑Bit Design

At the heart of the 68000 lies a 32‑bit instruction set and 32‑bit general‑purpose registers (eight data registers D0–D7 and eight address registers A0–A7, with A7 serving as the stack pointer). However, despite these 32‑bit features, the internal data path for arithmetic and logical operations is only 16 bits wide.

In practice, this means that operations on 32‑bit numbers are performed by sequentially processing the high and low 16‑bit halves. This “16/32‑bit” approach not only reduces the complexity of the ALU circuitry but also minimizes the overall transistor count—a design decision that contributed to improved manufacturing yields and lower production costs.

Data and Address Buses

Externally, the processor uses a 16‑bit data bus, so memory accesses occur in 16‑bit (word) units, though it supports byte accesses via data strobes.

The address bus is 24 bits wide; while internal address computations occur using 32‑bit arithmetic, only the lower 24 bits are available on the physical pins.

This design yields a flat memory model with a maximum addressable space of 16 MB without the complications of segmentation, simplifying both operating system design and application programming.

But this gave trouble with later CPU models as it was a common trick for programs to store data in the 4th byte of an address (which simply would be ignored).

Register Structure

The 68000’s register file is one of its most celebrated features. It provides:

• Data Registers (D0–D7): These are 32 bits wide and are used for general-purpose arithmetic and logical operations. However, when operating on byte or word data, only the lower 8 or 16 bits are affected.
• Address Registers (A0–A7): Also 32 bits wide, these registers are used for pointer operations and addressing modes. A7 doubles as the stack pointer (SP), and separate supervisor (SSP) and user (USP) stacks are supported in privileged modes.
• Status Register (SR): This 16‑bit register comprises an 8‑bit system byte (accessible only in supervisor mode) and an 8‑bit user byte known as the condition code register (CCR).
  • The CCR contains the standard flags—zero (Z), carry (C), overflow (V), negative (N), and extend (X).
  • The 3 least significant bits (bits 8, 9 and 10) of the Status register’s System byte form the interrupt mask. The interrupt priorities are numbered from 1 to 7, with level 7 having the highest priority. The level 7 interrupt is nonmaskable and thus cannot be disabled.
  • Bit 13 of the status register is the S flag, which specifies whether the MC68000 is in supervisor mode or user mode.
  • Bit 15 of the status register is the T flag, which specifies whether the MC68000 is in trace mode. After each instruction is executed in the trace mode, a trap is forced so that a debugging program can monitor the results of that instruction’s execution.

Privilege Modes

The processor operates in one of two modes of privilege: the "Supervisor" mode and the "User" mode. The privilege mode determines:

• which instructions are legal:
  • user programs are not permitted to execute the stop instruction or the reset instruction
  • to ensure that a user program cannot enter the Supervisor mode except in a controlled manner, the instructions which modify the whole state register are privileged
  • to aid in debugging programs which are to be used as operating systems, the move to user stack pointer (MOVE to USP) and move from user stack pointer (MOVE from USP) instructions are also privileged
• select between the Supervisor Stack Pointer (SSP) and the User Stack Pointer (USP) in instruction references
• and may by used by an external Memory Management Unit (MMU) to control and translate memory accesses

All exception processing is done in the Supervisor mode, regardless of the setting of the S bit. The bus cycles generated during exception processing are classified as supervisor references. All stacking operations during exception processing use the Supervisor Stack Pointer.

By enforcing a clear separation between User mode and Supervisor mode, the 68000 architecture provides:

• System security by preventing unauthorized execution of privileged operations
• Stability by ensuring that user programs cannot interfere with the operating system
• Support for multitasking and memory protection when integrated with an MMU

Instruction Set

The Motorola 68000 was renowned for its rich, orthogonal instruction set:

• Operand Flexibility: Instructions can operate on bytes (.b), words (.w), and long words (.l) without restrictions imposed by the addressing mode. Even though arithmetic is executed in 16‑bit chunks, the compiler and assembly programmer can manipulate 32‑bit values seamlessly.
• Addressing Modes: The 68000 supports an extensive range of addressing modes—including register direct, register indirect (with post‑increment, pre‑decrement, offset, and index variations), immediate, absolute, and PC‑relative addressing—which enhances code density and simplifies the generation of position‑independent and reentrant code.
• Dyadic Operations: Most operations in the 68000’s CISC architecture are dyadic (i.e. they have a source and a destination), enabling complex operations in fewer instructions compared to earlier 8‑bit designs. In contrast, many arithmetic and logical operations on the Z80 CPU are designed around the accumulator register (A).

This comprehensive and flexible instruction set was one of the reasons the 68000 became popular in systems that required multitasking and graphical interfaces, such as early Macintosh and Amiga computers.

Links

• Motorola MC68000 CPU User's Manual
• MC68000 Advance Information
• 68000 - Programmer's Instant Reference Card
• Decoding m68k opcodes
• Part 1 Part 2 Part 3 Design philosophy behind Motorola's MC68000
• Full list of 68k patents
• 68k instructions timings
• Yet Another Cycle Hunting Table
• Instruction Prefetch documentation
• Tech topic about a microcode-level 68000 core
• Tom Harte's SingleStepTests