Changes

Jump to: navigation, search

Gate Array

7,102 bytes added, 30 May
correction of an error relating to IC
[[File:Amstrad 40007 Gate Array .png|right|thumb|Amstrad 40007 Gate Array]][[File:Amstrad 40010 Gate Array.png|right|thumb|Amstrad 40010 Gate Array]]
Also designated as Video gate Gate Array (VGA, not to be confused with the IBM PC compatible graphic card spec).
<br>
In the [[KC Compact]] system, the functions of the Gate Array are "emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.
In the "cost-down" version of the CPC6128, the functions of the Gate Array are integrated into a an ASIC.  The Gate Array is described here is the one found in a standard CPC.
<br>
== What does it do? ==
The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), bus arbitration, DRAM refresh, interrupt generation and memory arrangement.
<br>
== Interrupt management Bus arbitration ==
Interrupts on the CPC are created by the The Gate Array based on settings from arbitrates access to the RAM between the CPU and the video hardware (CRTC. The and Gate -Array has an internal counter (R52) that counts from 0 to 51, incrementing after each HSYNC signal.
R52 will return to 0 and the Gate Array will send an interrupt request on any of these conditionsEvery microsecond:* When The CRTC generates a memory address using it exceeds 51's MA and RA signal outputs. See the [[CRTC]] wiki page to know how the motherboard wiring transforms these signals into the Video Memory Address (VMA).* By setting bit4 of the RMR register of the The Gate Array to 1fetches 2 bytes for each address. /CPU_ADDR is a 1MHz signal. So these 2 bytes are fetched sequentially. They are not interleaved with Z80 access. These bytes are fetched even when the border is on as this is required for DRAM refresh.* At the end of the 2nd HSYNC after the start of The video hardware is given priority so that the VSYNCdisplay is not disrupted.
When the The Gate -Array sends an interrupt request:*If generates the interrupts were authorized at "READY" signal which is connected to the time "/WAIT" input signal of the request, then bit5 of R52 CPU. This signal is cleared (but R52 was reset used to 0 anyway) and stop the interrupt takes placeCPU accessing RAM while the video-hardware is accessing it.*If interrupts are not authorizedIn fact, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using allows the EI instruction) and '''after Z80 to access the RAM in only 1 out of every 4 cycles. As a result, all instruction timings are stretched so that follows EI''' they are all multiples of a microsecond (so not immediately after EI1µs), bit5 and this gives an effective CPU clock of R52 3.3Mhz. Unlike the ZX Spectrum or the Amiga, where bus arbitration is cleared restricted to the "contended memory" or "chip RAM", on the CPC it also applies to ROM access and to RAM expansions. So the interrupt takes placeZ80 always runs at the same speed, regardless of the type of memory being accessed. Last but not least, bus arbitration also applies to I/O access. And memory access is not aligned with I/O access on Z80. Note: On Amstrad Plus, the ASIC also has to handle DMA instruction fetch from RAM.
<br>
== CSYNC signal DRAM refresh ==
On Amstrad CPC, the HSYNC and VSYNC signals are received from the [[CRTC]]. These signals are then modified by the Gate Array as Cis responsible for the DRAM refresh, instead of using the Z80 built-HSYNC and C-VSYNC and then merged into a single CSYNC signal in DRAM refresh mechanism. The reason is that will there can only be sent to 3 DRAM accesses per microsecond on this architecture. Doing DRAM refresh on each M1 cycle as it is done on MSX would bog down the displayCPU speed on CPC given its bus arbitration scheme.
When CRTC HSYNC is active, the Gate Array immediately outputs the palette colour blackThe Z80 generates a maximum of one request per microsecond. If the HSYNC is set to 14 characters then black will be output The CPC also requires two memory accesses per microsecond for 14µsreading video data.
If The CPC specs 4164-20 DRAMs. These require 330nS for a graphics mode change is pending, read or write cycle. The CPC also uses the HSYNC pulse width needs optimised sequential CAS cycles to be at least 2µs for Gate Array to change read the graphics modetwo video data bytes in half a microsecond.[https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/the-cpc-revision-zero-article/msg243769/ Source]
The HSYNC is modified before being sent way to cause the monitor. It happens 2µs after activation RAM refresh to fail in both a Plus or normal CPC is simply to stop a few bits of the CRTC HSYNC and stay a maximum of 4µs address changing (signal is cut short if HSYNC width is greater than 6ie. never refresh the selected area).
For exampleGenerally, if CRTC R2=46only the Row address needs to be cycled, so stopping MA0 through MA7 from changing, and CRTC HSYNC width is 14 chars then monitor hsync starts at 48 and lasts only until 51 includedstopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source]
The same logic applies to VSYNC, with lines instead of chars. The Gate Array VSYNC is considered complete when the 26th line has been processed. Then the Gate Array stops outputting the palette colour black.<br>
The Gate Array uses 2 internal counters to create its CSYNC signal== Interrupt generation ==[https:* H06 which counts the number of CRTC characters processed during an HSYNC//www. H06 is incremented by the Gate Array for each CRTC character when CRTC HSYNC is activegrimware. The Gate Array activates the C-HSYNC signal when H06 reaches 2, and changes its graphics mode if a change was pendingorg/doku. It deactivates this signal when H06 reaches 6.* V26 which counts the number of HSYNCs occuring during a VSYNC. V26 is incremented by the Gate Array when the CRTC signals an end of HSYNC. The Gate Array activates the C-VSYNC signal when V26 reaches 2. It deactivates this signal when V26 reaches 6php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)]
The HSYNC signal from CPU maskable interrupts are generated by the CRTC Gate Array. This is 0 when inactive done by using a 6bits internal counter and 1 when active. Same for VSYNCmonitoring the HSync and VSync signals produced by the CRTC.
C-HSYNC and C-VSYNC are composited using On every falling edge of the XNOR function. The resulting CSYNC HSync signal produced , the Gate Array will increment the counter by one. When the counter reaches 52, the Gate Array is 1 when inactive raise the INT signal and 0 when activereset the counter. With 50Hz PAL CRTC settings (one HSync every 64us) this will produce a 300Hz interrupt rate.
On a CPC monitor, When the CPU acknowledge the CSYNC is rendered in "absolute black"interrupt (eg. It it is darker than going to jump to the palette colour black output by interrupt vector), the Gate Array. The electron beam is basically turned off. Turning up will reset bit5 of the brightness level woncounter, so the next interrupt can't make it any brighteroccur closer than 32 HSync.
<brWhen a VSync occurs, the Gate Array will wait for two HSync and: * If the counter>=32 (bit5=1), then no interrupt request is issued and counter is reset to 0.* If the counter<32 (bit5=0), then an interrupt request is issued and counter is reset to 0. This 2 HSync delay after a VSync is used to let the main program, executed by the CPU, enough time to sense the VSync (for synchronisation with the display, most likely) before an interrupt service routine is eventually executed. So all the interrupt timings are mostly determined by the CRTC settings. Other than that, the internal interrupt counter can be cleared anytime by software using the Gate Array RMR register. The falling edge of the HSync trigger the counter, therefore modifying the duration of the HSync with the CRTC Register 3 can delay the interrupt requests by a few microseconds. This can be used to adjust interrupt timings between CPC and Plus machines…  Note: On Amstrad Plus, the interrupt management system is seriously beefed up. See the [[ASIC]] wiki page. === Timings ===[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)] The INT signal (active low) produced by the Gate Array, is a short pulse of 1.4us and starts right after the falling edge of the HSync signal (produced by the CRTC).  === DI in peace ===[https://acpc.me/ACME/FANZINES Source: Amslive No4 (Madram)]  The GA maintains its int request until it is accepted.RST #38 occurs not after the EI, but after the instruction following the EI (the Z80 needs time to clean up its act). Even if the int isn't validated by the Z80, IC (interrupt counter) continues on its merry way.But after the EI, a test similar to the one seen for the VBL is performed: The interrupt is generated anyway, but:* If IC < 32, IC is unchanged (the next int will then be produced 21 to 52 lines later).* Otherwise bit 5 of IC is set to zero.
== Controlling the Gate Array ==
The recommended I/O port address is &7Fxx.
 
The Gate Array is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. If you execute an I/O read operation on the Gate Array I/O address, the Gate Array will read an unpredictable value from the databus which will be in high-impedance state. If the value is a valid Gate Array command, it will be executed, otherwise nothing will happen. [https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml Source]
The function to be performed is selected by writing data to the Gate Array, the first bits of the data define the function selected (see table below). It is not possible to read from the Gate Array.
{|{{Prettytable|width: 700px; font-size: 2em;}}|-class="wikitable"
!colspan=4| 8bit command
!rowspan=2| Machine
| 1 || 0 || 0 || style="text-align: center;" | n || All || RMR || Control Interrupt counter, ROM mapping and Graphics mode || Gate Array
|-
| rowspan="2"| 1 || rowspan="2"| 0 || rowspan="2"| 1 || style="text-align: center;" rowspan="2" | n || All || RMR || ''Ghost register'' || Gate Array (CPC) or locked ASIC (Plus)
|-
| 1 || 0 || 1 || style="text-align: center;" | n || Plus || RMR2 || ASIC & Advanced ROM mapping || Unlocked ASIC
|-
| 1 || 1 ||colspan=2 style="text-align: center;" | n || All || MMR || Memory RAM memory mapping || PAL(only with 128KB or RAM expansion)
|}
In the CPC464, CPC664 and KC compact, MMR is performed in an external memory expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then MMR is not available.
In the CPC6128, MMR is performed by a [[PAL16L8|PALchip]] located on the main PCB, or an external memory expansion.
In the 464+ and 6128+, MMR is performed by the ASIC or an external memory expansion. Please read the document on RAM management for more information.
== Registers ==
Note: The Plus palette capabilities are only accessible through the [[Default I/O Port Summary|ASIC I/O page]]. Registers PENR and INKR are not needed in that case. === Register 0 - Palette Index PENR (Pen selectionSelect a color register) ===
When bit 7 and bit 6 are set to "0", the remaining bits determine which pen is to have its colour changed. When bit 4 is set to "0", bits 3 to 0 define which pen is to be selected. When bit 4 is set to "1", the value contained in bits 3-0 is ignored and the border is selected.
==== Summary ====
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"!Bit!Value!Function
|-
| ''Bit'' || ''Value'' || ''Function''|-| 7 || 0 || rowspan="2" | Gate Array function "Pen Selection"PENR register
|-
| 6 || 0
|}
<br> {|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-!Bit| ''Bit'' || ''!Value'' || ''!Function''
|-
| 7 || 0 || rowspan="2" | Gate Array function "Pen Selection"PENR register
|-
| 6 || 0
<br>
=== Register 1 - Palette Data INKR (Colour selectionChange the value of the currently selected color register) ===
Once the pen has been selected its colour can then be changed. Bits 4 to 0 specify the hardware colour number from the hardware colour palette.
==== Summary ====
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"!Bit!Value!Function
|-
| ''Bit'' || ''Value'' || ''Function''|-| 7 || 0 || rowspan="2" | Gate Array function "Colour selection"INKR register
|-
| 6 || 1
<br>
=== Register 2 - Select screen mode and RMR (Control Interrupt counter, ROM configuration mapping and Graphics mode) ===
This is a general purpose register responsible for the [[Video modes|screen graphics mode]] and the ROM configuration.
==== Screen Graphics mode selection ====
The function of bits 1 and 0 is to define the screen mode. The settings for bits 1 and 0 and the corresponding screen mode are given in the table below.
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit 1'' || ''!Bit 0'' || ''!Screen mode''
|-
| 0 || 0 || Mode 0, 160x200 resolution, 16 colours
==== ROM configuration selection ====
Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &amp;0000-&amp;3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &amp;0000-&amp;3FFF will return data in the ROM. When a value is written to &amp;0000-&amp;3FFF, it will be written to the RAM underneath the RAMROM. When it is disabled, data read from &amp;0000-&amp;3FFF will return the data in the RAM.
Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &amp;C000-&amp;FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &amp;c000-&amp;ffff, will return data in the ROM. When data is written to &amp;c000-&amp;FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &amp;c000-&amp;ffff it will be the data in the RAM.
Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.
==== Summary ====
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|-| ''!Bit'' || ''!Value'' || ''!Function''
|-
| 7 || 1 || rowspan="2" | Gate Array functionRMR register
|-
| 6 || 0
|-
| 5 || - || not used''must be 0 on Plus machines with ASIC unlocked''
|-
| 4 || x || Interrupt generation control
| 2 || x || 1=Lower ROM area disable, 0=Lower ROM area enable
|-
| 1 || x || rowspan="2" | Screen Graphics Mode slectionselection
|-
| 0 || x
<br>
=== Register 3 - RAM Banking RMR2 (ASIC & Advanced ROM mapping) ===
This register exists only in CPCs with 128K RAM (like the CPC 6128, Plus or CPCs with [[Standard Memory Expansions]]). Note: In the CPC 6128GX4000, and is only accessible when the register ASIC is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip. See its wiki pageunlocked.
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"!Bit!Value!Function
|-
| ''7 || 1 || rowspan="3" | Gate Array RMR2 register|-| 6 || 0|-| 5 || 1|-| 4 || x || rowspan="2" |RMR addressing mode|-| 3 || x|-| 2 || x || rowspan="3" | Physical ROM number (0..7)|-| 1 || x|-| 0 || x|} {| class="wikitable"|+ RMR addressing modes!Bit'' 4!Bit 3!Lower ROM![[ASIC|ASIC I/O page]]| ''Value'' -|0| ''0|&0000-&3FFF|Disabled|-|0|1|&4000-&7FFF|Disabled|-|1|0|&8000-&BFFF|Disabled|-|1|1|&0000-&3FFF|&4000-&7FFF|} The physical ROMs are also accessible as upper ROMs by using the [[Upper ROM Bank Number]] port and the RMR register. <br> === Register MMR (RAM memory mapping) === This register exists only in CPCs with 128K RAM (like the CPC 6128), or CPCs equipped with [[Standard Memory Expansions]]. Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip. {| class="wikitable"!Bit!Value!Function''
|-
| 7 || 1 || rowspan="2" | Gate Array function 3MMR register
|-
| 6 || 1
|-
| 5 || b x || rowspan="3" |64K bank number (0..7); always 0 on an unexpanded CPC6128, 0-7 on [[Standard Memory Expansions]]
|-
| 4 || bx
|-
| 3 || bx
|-
| 2 || x || rowspan="3" | RAM Config (0..7)
== Video memory structure ==
{|{{Prettytable|width: 700px; font-size: 2em;}}class="wikitable"|!rowspan=2|'''Graphics Mode'''||!colspan=8 style="text-align: center;"|'''VRAM byte'''||!colspan=8 style="text-align: center;"|'''Displayed Pixels'''!rowspan=2|Definition!rowspan=2|Pixel clock!rowspan=2|'''Definition'''Default resolution
|-
|'''!7'''|'''!6'''|'''!5'''|'''!4'''|'''!3'''|'''!2'''|'''!1'''|'''!0'''|'''!1'''|'''!2'''|'''!3'''|'''!4'''|'''!5'''|'''!6'''|'''!7'''|'''!8'''
|-
|0
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 16 colorscolours|4 MHz|160x200, 20-column text
|-
|1
|colspan=2 style="text-align: center;"|D
|4 pixels in 4 colours
|8 MHz
|320x200, 40-column text
|-
|2
|G
|H
|8 pixels in 2 colorscolours|16 MHz|640x200, 80-column text
|-
|3
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 4 colorscolours|4 MHz|160x200, 20-column text
|}
To display a CPC image you will need to use a analogue monitor with a composite sync.
<br> === Palette sorted by Hardware Firmware Colour Numbers === The firmware colour palette is sorted by luminance value.
{| class="FCK__ShowTableBorderswikitable"
|-
| ''Hardware Number||Firmware Number|| ''Colour Name''
| ''R&nbsp;%'' || ''G&nbsp;%'' || ''B&nbsp;%'' || ''Colour''
|-
| 0 (40h) || 13 || White || 50|| 50|| 50|| bgcolor="#808080" | !Firmware Number!Hardware Number!Colour Name!R %!G %!B %!ASIC!Colour
|-
| 1 (41h) 0|| (13) 54h || White Black || 50 0|| 50 0|| 50 0|| #000|| bgcolor="#808080000000" |
|-
| 2 1|| 44h (42hor 50h) || 19 Blue || Sea Green 0|| 0||10050|| 50#006|| bgcolor="#00ff80000080" |
|-
| 3 (43h) 2|| 25 55h || Pastel Yellow Bright Blue ||100 0|| 0||100|| 50#00F|| bgcolor="#ffff800000ff" |
|-
| 4 (44h) 3|| 1 5Ch || Blue Red || 50|| 0|| 0|| 50#600|| bgcolor="#000080800000" |
|-
| 5 (45h) 4|| 7 58h || Purple Magenta ||10050|| 0|| 50|| #606|| bgcolor="#ff0080800080" |
|-
| 6 (46h) 5|| 10 5Dh || Cyan Mauve || 50|| 0|| 50100|| 50#60F|| bgcolor="#0080808000ff" |
|-
| 7 (47h) 6|| 16 4Ch || Pink Bright Red ||100|| 50 0|| 50 0|| #F00|| bgcolor="#ff8080ff0000" |
|-
| 8 (48h) 7|| 45h (7or 48h) || Purple ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" |
|-
| 9 (49h) 8|| (25) 4Dh || Pastel Yellow Bright Magenta ||100|| 0||100|| 50#F0F|| bgcolor="#ffff80ff00ff" |
|-
| 10 (4Ah) 9|| 24 56h || Bright Yellow Green ||100 0||10050|| 0|| #060|| bgcolor="#ffff00008000" |
|-
| 11 (4Bh) 10|| 26 46h ||Cyan || Bright White 0||10050||10050||100#066|| bgcolor="#ffffff008080" |
|-
| 12 (4Ch) 11|| 6 57h || Bright Red ||100Sky Blue || 0|| 050||100|| #06F|| bgcolor="#ff00000080ff" |
|-
| 13 (4Dh) 12|| 8 5Eh || Bright MagentaYellow ||10050|| 50|| 0||100#660|| bgcolor="#ff00ff808000" |
|-
| 14 13|| 40h (4Ehor 41h) || 15 White || Orange 50||10050|| 50|| 0#666|| bgcolor="#ff8000808080" |
|-
| 15 (4Fh) 14|| 17 5Fh || Pastel MagentaBlue ||10050|| 50||100|| #66F|| bgcolor="#ff80ff8080ff" |
|-
| 16 (50h) 15|| (1) 4Eh || Blue Orange || 0100|| 50|| 0|| 50#F60|| bgcolor="#000080ff8000" |
|-
| 17 (51h) 16|| (19) 47h || Sea Green Pink || 0100||10050|| 50|| #F66|| bgcolor="#00ff80ff8080" |
|-
| 18 (52h) 17|| 18 4Fh || Bright Green Pastel Magenta || 0100|| 50||100|| 0#F6F|| bgcolor="#00ff00ff80ff" |
|-
| 19 (53h) 18|| 20 52h || Bright Cyan Green || 0||100||100 0|| #0F0|| bgcolor="#00ffff00ff00" |
|-
| 20 19|| 42h (54hor 51h) || 0 || Black Sea Green || 0|| 0100|| 050|| #0F6|| bgcolor="#00000000ff80" |
|-
| 21 (55h) 20|| 2 53h || Bright Blue Cyan || 0|| 0100||100|| #0FF|| bgcolor="#0000ff00ffff" |
|-
| 22 (56h) 21|| 9 5Ah || Green Lime || 050|| 50100|| 0|| #6F0|| bgcolor="#00800080ff00" |
|-
| 23 (57h) 22|| 11 59h ||Pastel Green || Sky Blue 50|| 0100|| 50||100#6F6|| bgcolor="#0080ff80ff80" |
|-
| 24 (58h) 23|| 4 5Bh || Magenta Pastel Cyan || 50|| 0100|| 50100|| #6FF|| bgcolor="#80008080ffff" |
|-
| 25 (59h) 24|| 22 4Ah || Pastel Green Bright Yellow || 50100||100|| 50 0|| #FF0|| bgcolor="#80ff80ffff00" |
|-
| 26 25|| 43h (5Ahor 49h) || 21 Pastel Yellow || Lime 100|| 50100||10050|| 0#FF6|| bgcolor="#80ff00ffff80" |
|-
| 27 (5Bh) 26|| 23 4Bh || Pastel Cyan Bright White || 50100||100||100|| #FFF|| bgcolor="#80ffffffffff" | |} Note: We can observe that the official Amstrad names of some colours are a bit silly: "red" is in fact brown, "yellow" is in fact khaki and "white" is in fact grey. <br> === Amstrad Colour Names === <gallery>Cpc 6128 master colour chat.jpg|Master colour chartCpc 6128 farbtabelle.jpg|FarbtabelleCpc 6128 palette des couleurs.jpg|Palette des couleursCpc 6128 tabla de colores.jpg|Tabla de colores</gallery> <br> === Palette sorted by Hardware Colour Numbers === {| class="wikitable"
|-
| 28 (5Ch) || 3 || Red || 50|| 0|| 0|| bgcolor="#800000" | !Hardware Number!Firmware Number!R %!G %!B %!ASIC!Colour!Colour Name!German Name!French Name!Spanish Name
|-
| 29 0 (5Dh40h) || 5 13 || Mauve 50|| 50|| 050||100#666|| bgcolor="#8000ff808080" | || White || Weiß || Blanc || Blanco
|-
| 30 1 (5Eh41h) || 12 (13) || Yellow 50|| 50|| 50|| 0#666|| bgcolor="#808000808080" | || White || Weiß || Blanc || Blanco
|-
| 31 2 (5Fh42h) || 14 19 || Pastel Blue 0|| 50100|| 50||100#0F6|| bgcolor="#8080ff00ff80" | || Sea Green || Seegrün || Vert marin || Verde marino|}- === Palette sorted by Firmware Colour Numbers === {| class 3 (43h) || 25 ||100||100|| 50|| #FF6|| bgcolor="FCK__ShowTableBorders#ffff80"| || Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| ''Firmware Number'' 4 (44h) || ''Hardware Number'' 1 || ''Colour Name'' 0| ''R&nbsp;%'' | 0| ''G&nbsp;%'' |50| ''B&nbsp;%'' |#006| ''Colour''| bgcolor="#000080" | || Blue || Blau || Bleu || Azul
|-
| 0 5 (45h) || 54h 7 ||Black 100|| 0|| 050|| 0#F06||bgcolor="#000000ff0080"||| Purple || Purpur || Pourpre || Púrpura
|-
| 1|| 44h 6 (or 50h46h) ||Blue 10 || 0|| 050|| 50|| #066||bgcolor="#000080008080"||| Cyan || Blaugrün || Turquoise || Ciano
|-
| 2 7 (47h) || 55h 16 ||Bright Blue 100|| 050|| 050||100#F66||bgcolor="#0000ffff8080"||| Pink || Rosa || Rose || Rosa
|-
| 3 8 (48h) || 5Ch (7) ||Red || 50100|| 0|| 050|| #F06||bgcolor="#800000ff0080"||| Purple || Purpur || Pourpre || Púrpura
|-
| 4 9 (49h) || 58h (25) ||Magenta 100|| 50100|| 050|| 50#FF6||bgcolor="#800080ffff80"||| Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 510 (4Ah) || 5Dh 24 ||Mauve 100|| 50100|| 0||100#FF0||bgcolor="#8000ffffff00"||| Bright Yellow || Hellgelb || Jaune vif || Amarillo brillante
|-
| 611 (4Bh) || 4Ch 26 ||Bright Red 100||100|| 0100|| 0#FFF||bgcolor="#ff0000ffffff"||| Bright White || Leuchtendweiß || Blanc brillant || Blanco brillante
|-
| 7|| 45h 12 (or 48h4Ch) ||Purple 6 ||100|| 0|| 50 0|| #F00||bgcolor="#ff0080ff0000"||| Bright Red || Hellrot || Rouge vif || Rojo brillante
|-
| 8|| 13 (4Dh ) ||Bright Magenta 8 ||100|| 0||100|| #F0F||bgcolor="#ff00ff"||| Bright Magenta|| helles Magenta || Magenta vif || Magenta brillante
|-
| 914 (4Eh) || 56h 15 ||Green || 0100|| 50|| 0|| #F60||bgcolor="#008000ff8000"||| Orange || Orange || Orange || Naranja
|-
|1015 (4Fh) || 46h 17 ||Cyan 100|| 050|| 50100|| 50#F6F||bgcolor="#008080ff80ff"||| Pastel Magenta|| Pastell-magenta || Magenta pastel || Magenta pastel
|-
|1116 (50h) || 57h (1) ||Sky Blue 0|| 0|| 50||100#006||bgcolor="#0080ff000080"||| Blue || Blau || Bleu || Azul
|-
|1217 (51h) || 5Eh (19) ||Yellow 0|| 50100|| 50|| 0#0F6||bgcolor="#80800000ff80"||| Sea Green || Seegrün || Vert marin || Verde marino
|-
|13|| 40h 18 (or 41h52h) ||White 18 || 50 0|| 50100|| 50 0|| #0F0||bgcolor="#80808000ff00"||| Bright Green || Hellgrün || Vert vif || Verde brillante
|-
|1419 (53h) || 5Fh 20 ||Pastel Blue 0|| 50100|| 50100||100#0FF||bgcolor="#8080ff00ffff"||| Bright Cyan || helles Blaugrün || Turquoise vif || Ciano brillante
|-
|1520 (54h) || 4Eh 0 ||Orange 0||100|| 50 0|| 0|| #0||bgcolor="#ff8000000000"||| Black || Schwarz || Noir || Negro
|-
|1621 (55h) || 47h 2 ||Pink 0||100 0|| 50100|| 50#00F||bgcolor="#ff80800000ff"||| Bright Blue || Hellblau || Bleu vif || Azul brillante
|-
|1722 (56h) || 4Fh 9 ||Pastel Magenta 0||10050|| 50 0||100#060||bgcolor="#ff80ff008000"||| Green || Grün || Vert || Verde
|-
|1823 (57h) || 52h ||Bright Green 11 || 0|| 50||100|| 0#06F||bgcolor="#00ff000080ff"||| Sky Blue || Himmelblau || Bleu ciel || Azul cielo
|-
|19|| 42h 24 (or 51h58h) ||Sea Green 4 || 50|| 0||10050|| 50#606||bgcolor="#00ff80800080"||| Magenta || Magenta || Magenta || Magenta
|-
|2025 (59h) || 53h 22 ||Bright Cyan 50|| 0100||10050||100#6F6||bgcolor="#00ffff80ff80"||| Pastel Green || Pastellgrün || Vert pastel || Verde pastel
|-
|21|| 26 (5Ah ) ||Lime 21 || 50||100|| 0|| #6F0||bgcolor="#80ff00"||| Lime || Limonengrün || Vert citron || Verde lima
|-
|2227 (5Bh) || 59h ||Pastel Green 23 || 50||100|| 50100|| #6FF||bgcolor="#80ff8080ffff"||| Pastel Cyan || Pastell-blaugrün|| Turquoise pastel|| Ciano pastel
|-
|2328 (5Ch) || 5Bh ||Pastel Cyan 3 || 50||100 0||100 0|| #600||bgcolor="#80ffff800000"||| Red || Rot || Rouge || Rojo
|-
|2429 (5Dh) || 4Ah 5 ||Bright Yellow 50||100 0||100|| 0#60F||bgcolor="#ffff008000ff"||| Mauve || Hellviolett || Mauve || Malva
|-
|25|| 43h 30 (or 49h5Eh) ||Pastel Yellow 12 ||10050||10050|| 50 0|| #660||bgcolor="#ffff80808000"||| Yellow || Gelb || Jaune || Amarillo
|-
|2631 (5Fh) || 4Bh 14 ||Bright White 50||10050||100||100#66F||bgcolor="#ffffff8080ff"||| Pastel Blue || Pastellblau || Bleu pastel || Azul pastel
|}
 
<br>
=== Intensities ===
The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).
 
On an actual Amstrad CPC, the half-intensity colour signal is measured to be closer to 40% rather than the expected 50%. This was verified by [[Grim]] and independently confirmed by [[Nocash]]. [https://www.grimware.org/doku.php/documentations/devices/gatearray#inkr Source]
* [[CPC Palette]] - some more details
=== To calculate This explains why the Amstrad engineers used the following values to adapt the old colour palette to the new 12-bit palette on the Amstrad Plus:* 0% became #0* 50% became #6. They specifically chose #6 for the 50% value ===instead of the expected #7 or #8, to better match the real Amstrad CPC palette.* 100% became #F
'''Red''' <br>
0% =&gt; do not add anything == Green Screen Colours ===
50% =&gt; add 3 On a green screen, where all colours are shades of unsaturated green, the firmware colours are in order of increasing intensity. Black is darkest green, bright white is brightest green, and firmware colour 13 is a medium green.
100% =&gt; add The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. Amstrad preferred to propose a completely different image system, not comparable to a conversion to monochrome, which would have limited the number of brightness levels to 21 (for example, colours 9 and 6 would have had the same luminance).
'''Green''' They opted for a table of 27 linear brightness steps. They assigned values of 1 (1kΩ) for blue, 3 (3.3kΩ) for red, and 9 (10kΩ) for green.
0% =&gt; do not add anything === To calculate the luminance value ====
50% =&gt; add 9 '''Red'''
*0% =&gt; do not add anything *50% =&gt; add 3 *100% =&gt; add 18 6
'''BlueGreen'''
*0% =&gt; do not add anything *50% =&gt; add 9 *100% =&gt; add 18
50% =&gt; add 1 '''Blue'''
100*0% =&gt; do not add 2 anything *50% =&gt; add 1 *100% === Green Screen Colours === On a green screen (where all colours are shades of green), the colours (in BASIC colours), are in order of increasing intensity. Black is very dark, and white is bright green, and colour 13 is a medium green. (Thanks to [[Mark Rison|Mark Rison]] for this information) The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. We have other values. Amstrad preferred to propose a completely different image system, not comparable to a conversion to monochrome, which would have limited the number of brightness levels to 21 (for example, colours 9 and 6 would have had the same luminance). They opted for a table of 27 linear brightness steps. They assigned values of 1 (1kΩ) for blue, 3 (3.3kΩ) for red, and 9 (10kΩ) for green.&gt; add 2
<br>
Image:40226_am4_metal.jpg|40226 PreASIC Metal Layer
</gallery>
 
[[File:Ga.pinout.40007.png]] [[File:Ga.pinout.40008.40010.png]]
 
Note: Some CPC motherboards can accommodate both types of Gate Array pinouts. [https://thecheshirec.at/2024/10/06/il-existe-une-carte-multi-gate-array-et-cest-amstrad-qui-la-faite/ Source]
<br>
==See alsoExternal links ==*[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]* [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Gate Array documentation in Amstrad CRTC Compendium]* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]
*[[Gate Array and ASIC Pin-Outs]]<br>
*[[Video modes]] : for other informations on colours and pixels.==See also==
*[[CRTCGate Array and ASIC Pin-Outs]]*[[PAL16L8]] : the other video stuff.for RAM arrangement
*[[ASIC]] : for Plus users
*[[CRTC]] : the other video stuff
*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.
*[[Media:40010-simplified V03.pdfVideo modes]] [https://wwwfor other informations on colours and pixels.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Forum thread] Gate Array schematics - reverse engineered by Gerald
<br> == External links ==*[[Media:40010-simplified V03.pdf]] [https://bread80www.comcpcwiki.eu/2021forum/06/03/understanding-the-amstrad-cpc-video-ram-and-hardware/gate-array-subsystemdecapped!/ Electronic signals analysis of the Gate Array by Bread80]* [https:msg170713//www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware#msg170713 Forum thread]* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]schematics - reverse engineered by Gerald
[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]][[Category:CPC Internal Components]][[Category:Electronic Component]]
Longshot
463
edits
Retrieved from "https://www.cpcwiki.eu/index.php/Special:MobileDiff/117157...126306"