Changes
CRTC
,UM6845:
Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
UM6845R:
Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
MC6845:
Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
Pre-ASIC/ASIC:
Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
== Interlace and Skew (R8) ==
UM6845:
Bits 7..6 define the delay of the CUDISP signal.
Bits 5..4 define the delay of the DISPTMG signal.
Bits 3..2 are ignored.
Bits 1..0 define the interlace mode.
UM6845R:
Bits 7..2 are ignored.
Bits 1..0 define the interlace mode.
MC6845:
Bits 7..2 are ignored.
Bits 1..0 define the interlace mode.
Pre-ASIC/ASIC:
Bits 7..6 are ignored.
Bits 5..4 define the delay of the DISPTMG signal.
Bits 3..2 are ignored.
Bits 1..0 define the interlace mode.
== UM6845R and R31 ==
