Changes
/* I/O Map and NMI Overview */
rrrr is reg number
D[7..0] Data
F9DX 0 0 1 0 (1) 0 r r -W TIMER [[8253 chip|8254 ]] CHANNELS 0,1,2
rr is reg number
D[7..0] Data
F9DY 0 0 1 0 0 (1) r r -W TIMER [[8253 chip|8254 ]] CHANNELS 3, and DAC
nn is reg number
D[7..0] Data
