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/* Technical */
The bug is related to logic around link LK106 and IC IC116 near the Z80 which relates to the Z80 signals /IORQ, /RESET, A13 and /WAIT, but the exact reason this logic is here is not known.
See [[http://www.cpcwiki.eu/imgs/8/84/CPC_Plus_CPU_Schematic.jpg]]
Logic analysis:
See [[http://www.cpcwiki.eu/index.php/File:IM2_Plus_Ack_Bug.png]]
When a raster interrupt is pending it has been found that the ASIC sees two interrupt acknowledge from the Z80.
