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CPC 464 prototype with Gate Array simulator board found

Started by balford, 11:58, 27 October 21

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eto

And here a user replicated the Gate Array using 2 Raspberry Picos: https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/creating-a-replacemant-gate-array/


Not released yet, but it looks also very promising.

Joseman

Quote from: gerald on 08:29, 30 November 21
I have a working GA replacement, unfortunately component availability problem just can't make it happen ... yet  ;)
https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/a-minimal-gate-array/msg198585/#msg198585
great!
and is 100% accurate or that board will help to understand something missing?

TotO

Quote from: Joseman on 20:39, 29 November 21
That Gate Array board, is the best option to clone de GA?
Not at all, because it doesn't work exactly like the final product.
The best is the retro-engeenering from the commercial version done by gerald.
"You make one mistake in your life and the internet will never let you live it down" (Keith Goodyer)

ralferoo

Quote from: gerald on 16:14, 27 October 21Yes, at least 9 of them. But if these are just PAL (not using registers) it should be doable. With registers it will just make it a bit more complicated.
However the SOLD AS SEEN UNTESTED (MAY NOT WORK) is a big showstopper for me.
It's pretty hard to extract the configuration data out of a PLA IIRC, so even if you know the exact chip that was used and have the datasheet, it might not do you much good.

I'm not sure there's all that many secrets left in the GA though... I remember when doing my FPGA-based emulator, I was convinced the _WAIT logic was really complicated, after having a long argument with someone who was doing a software emulator (I forget who now) and trying out what they said, I discovered they were right and the really simple way also yields exactly the same timing weirdnesses. (Although checking my code now shows I kept my overly complicated logic involving different rules that handles _IORQ and _MREQ differently depending on _M1, but I can't remember why now, probably just because it also seemed to work on everything I'd tried).

I think the most complicated logic in the entire gate array is the colour palette decoding, as it seems quite horrible and arbitrary, but when I sat down for a couple of hours with pen and paper and analysed the logic patterns I ended up with something pretty simple. Digging out the snippet from my code:

        r_v     <= '1' when col(3)='1' or (col(4)='0' and col(0)='1') else '0';
        r_oe    <= '1' when (col(4)='1' and col(3)='1') or (col(4)='0' and col(3)='0' and col(2)='0' and col(1)='0') else '0';

        g_v     <= '1' when col(2)='0' and (col(1)='1' or col(0)='1') else '0';
        g_oe    <= '1' when (col(2)='1' and col(1)='1') or (col(2)='0' and col(1)='0' and col(3)='0' and col(4)='0') else '0';

        b_v     <= col(0);
        b_oe    <= '1' when (col(4)='0' and col(3)='0') or (col(2)='0' and col(1)='0') else '0';


Where _v is the high/low output on the pin, _oe is the output enable, when it's 1 the pull-up/pull-down resistor combo leave the pin floating at half voltage.

I also made similar discoveries with this when I really sat down to think about how I'd implement the sound chip in as few gates as possible. My entire AY8912 implementation was in the order of 300 gates, and smaller than most implementations use for their volume lookup table! (And it emulated the bugs in the real chip too, which is always a bonus!)

Extra detail: unlike every other implementation which use an 8-bit DAC, the output of my AY8912 implementation was a single-bit DAC that was then smoothed with a small capacitor. The volume response sounded identical to compared to all the complicated software versions with their fancy lookup tables, but I'm not hard-core audiophile enough to know if it sounds exactly the same to everyone else! But I was running that at 16MHz and IIRC the real chip only takes a 1MHz clock, so I probably wasn't doing it exactly the same.

ralferoo

Quote from: eto on 09:42, 30 November 21And here a user replicated the Gate Array using 2 Raspberry Picos: https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/creating-a-replacemant-gate-array/

This seems kind of excessive. There's probably more logic in the power-control circuitry on the RPi than the entire GA it's emulating!

eto

Quote from: ralferoo on 16:43, 01 December 21There's probably more logic in the power-control circuitry on the RPi


Raspberry Pico, not Raspberry Pi






ralferoo

Quote from: eto on 19:02, 01 December 21
Raspberry Pico, not Raspberry Pi
My argument is probably still true, but yeah I'd overlooked the fact that at least it's the embedded controller thingy and not a Pi.

pelrun

I don't understand the desire for "gate efficiency" - when the hardware in question is $1, does it really matter if half the gates in it are unused? All the alternatives cost far more - and that's an actually useful metric compared to something that's effectively unmeasurable.

TotO

I think the idea was to use disproportionate measures to reach the goal.
"You make one mistake in your life and the internet will never let you live it down" (Keith Goodyer)

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