Real Time Clock Board

[GUNHED]

The Dobbertin can be installed on any rom.
How do you know at what address you can find it?

You just check if you can read from it. Or save a single byte which does indicate the ROM number. 

[Pollo]

If it sounds like a kludge and it feels like a kludge, it is a kludge 

[d_kef]

Just reading (writing) from (to) an address in the memory.

This of course means that you do need additional logic for paging in the RTC.
The only difference is that you take /MREQ into account instead of /IOREQ. But since the ULIFAC already has a ROM/RAM paging mechanism in place, it should be easier.

d_kef

[GUNHED]

If it sounds like a kludge and it feels like a kludge, it is a kludge 

So a Commercial product is just a kludge for you? Which kludge RTC would you suggest to be used then? 

[GUNHED]

Just reading (writing) from (to) an address in the memory.

This of course means that you do need additional logic for paging in the RTC.
The only difference is that you take /MREQ into account instead of /IOREQ. But since the ULIFAC already has a ROM/RAM paging mechanism in place, it should be easier.

d_kef

As a software person I don't know about this in detail. The original product from Dobbertin was just to be put into any kind of EPROM socket. Very easy for the user that way. 

[Pollo]

If it sounds like a kludge and it feels like a kludge, it is a kludge 

So a Commercial product is just a kludge for you? Which kludge RTC would you suggest to be used then?

SF2 and Nova are both straightforward.
SF2 is best for existing software support though.

[GUNHED]

If it sounds like a kludge and it feels like a kludge, it is a kludge 

So a Commercial product is just a kludge for you? Which kludge RTC would you suggest to be used then?

SF2 and Nova are both straightforward.
SF2 is best for existing software support though.

Well, that's your opinion. I guess it's best to leave the decision to @ikonsgr 

[ikonsgr]

Ok, i suppose the best approach (in terms of cost, availability, software support and ease of implementation on ULIfAC II board) is to go for Dobbertin's smart watch.
Now, i took a look at the datasheet and it seems that only a handful of signals need connection to the board (since there will be no actual rom chip seated above, but instead use the rom board of ULIfAC to mount the required time-rom):
You cannot view this attachment.
 
According to this: https://pelrun.github.io/cpc-schematics/index.html ,and assuming that originally the adapter was seated on Amstrad's CPC upper rom socket of a rom board (e.g. like 40015 Amsdos Rom):
- DS1216 pin 27 (WE) goes to 5v 
- DS1216 pin 26 (VccB) goes to A13
- DS1216 pin 20 (CE)  goes to RomeEn of Expansion port
- DS1216 pin 22 (OE)  goes to a pin of ic210 (74LS132)
- DS1216 pin 1 (RST) goes to 5v
The rest pins are obvious (D0, A0, A2 and power supply).
I don't know if the above are correct, but my biggest concern is where should i connect the pin 22 (OE signal) of DS1216, maybe connect it to Gnd (always active)?
@GUNHED you seem to know a lot about this, hope you can help 

Just reading (writing) from (to) an address in the memory.

This of course means that you do need additional logic for paging in the RTC.
The only difference is that you take /MREQ into account instead of /IOREQ. But since the ULIFAC already has a ROM/RAM paging mechanism in place, it should be easier.
d_kef

I thought that this is done using RSX commands from the Time rom,  so no extra logic would be needed. Also if extra logic is needed, how the original Dobbertin's RTC worked as it was consisted only from the DS1216 adapter+ time rom above?

[GUNHED]

Great choice!!! 

Well, I still have the Source-Code of the Time-ROM, just in case you want to change / adapt / extend it or whatever 

Also let me know if I can help in any way (software part). 

[ikonsgr]

Great choice!!! 

Well, I still have the Source-Code of the Time-ROM, just in case you want to change / adapt / extend it or whatever 

Also let me know if I can help in any way (software part). 

Well, my needs are mostly hardware , as i need to know the exact connections of the DS1216 to Amstrad board, and also if an extra logic is needed, although from what it's noted here: https://www.cpcwiki.eu/index.php/Dobbertin_Smart_Watch ,the original Dobbertin's Smart watch didn't have any extra logic apart from the DS1216 and the time rom.

[d_kef]

I thought that this is done using RSX commands from the Time rom,  so no extra logic would be needed. Also if extra logic is needed, how the original Dobbertin's RTC worked as it was consisted only from the DS1216 adapter+ time rom above?

My understanding is that you MUST have also the TIMER ROM+ installed on top of the DS1216. The TIMER ROM and the DS1216 are both using the same ROM number.
When you want to access the RTC then you select the TIMER ROM, activate the CPC upper ROM and then you send an "activating sequence". As soon as the DS1216 gets the activating sequence it disables access to the ROM and you can read or write the 8 bytes of clock data. Otherwise you access the TIMER ROM data.

So back in the day the DS1216 and the ROM was just placed in an empty slot of your ROM board and you could use it imediately. If you don't have a physical ROM board (the case of ULIFAC) then you have to be creative....

d_kef

[Pollo]

Looking at the SF2 chip more closely, it is not that rosy. The RTC chip is quite bloated: it has a square wave generator, an interrupt generator and many status registers.

And the Nova chip looks so nice, I have to admit. 32KB NVRAM for the CPC devs and a simple RTC with clean hardware access, even from Basic. No rom needed.

The TimerROM+ is mandatory for the Dobbertin to be used from Basic.

[d_kef]

The TimerROM+ is mandatory for the Dobbertin to be used from Basic.

Not only from Basic.
I think that detecting the ROM number of the TimeROM+ (the presence of the ROM itself) is the only way to know that the RTC is present and communicate with it.
Maybe @GUNHED and @Prodatron can confirm this.

d_kef

[ikonsgr]

Ok then, can someone explain how exactly this disabling of time rom is done? 
The Recognition Pattern noted: C5h, 3Ah, A3h, 5Ch, C5h, 3Ah, A3h, 5Ch
Are a sequence of reading time rom addresses at: C0C5h, CO3Ah, COA3h, CO5Ch, COC5h, CO3Ah, COA3h, CO5Ch ?
 And when this happens  the time rom is "disabled" and the DS1216 time chip is enabled by activating DS1216 CS signal ) and then you can access registers by read/write at any memory addresses having specific A0,A2 and D0 signals?
So is it right to assume that i have  to treat the time chip like reading/writing to memory addresses instead of treating it as rom?

[ikonsgr]

When you want to access the RTC then you select the TIMER ROM, activate the CPC upper ROM and then you send an "activating sequence".

Does this practically means sequential reading of time rom at the specific 8 addresses of the pattern: C0C5h, CO3Ah, COA3h, CO5Ch, COC5h, CO3Ah, COA3h, CO5Ch?

As soon as the DS1216 gets the activating sequence it disables access to the ROM and you can read or write the 8 bytes of clock data. Otherwise you access the TIMER ROM data.

How exactly you do that? Activate the CS signal of DS1216 for the next 8 memory reads/writes ( at any memory addresses having specific A0,A2 and D0 signals)  and then disable it again?

[d_kef]

According to the DS1216 datasheet:

Communication with the SmartWatch RAM is established by pattern recognition on a serial bit stream of 64 bits that must be matched by executing 64 consecutive write cycles containing the proper data on DQ0. On the SmartWatch ROM, communication with the clock is established using A2 and A0, and either OE or CE. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory. After the pattern match, the next 64 reads and/or writes are directed to the clock, and the RAM is disabled. Once the pattern is established, the next 64 read/write cycles will be directed to the RTC registers. When power is cycled, 64 reads should be executed prior to any writes to ensure that the RTC registers are not written. A pattern match is ignored if the RST bit is zero and the RST pin goes low during the match sequence. A pattern match is also terminated if a read occurs during the 64-bit match sequence.

and

Communication with the SmartWatch is established by pattern recognition of a serial bit stream of 64 bits that must be matched by executing 64 consecutive write cycles, placing address bit A2 low with the proper data on address bit A0.

So you need to read a byte from address #C000 in order to write a 0 and read a byte from #C001 to write a 1. You do 64 reads for the 64 bits of the recognition pattern.

Fully working smart watch routines have been published by @GUNHED here.
I tested them and work just fine with WinAPE emulator.

d_kef

[Prodatron]

It is more convenient from an hardware standpoint.
But less convenient from a software standpoint.

You are right, it's more easy to read/write from the SF2 RTC compared to the Dobbertin. For the Dobbertin you have the additional ROM switches and these heavy bit-shiftings. That makes the code significant larger.
But as you won't request the RTC more often than every 50. frame this doesn't have a big impact.

[ikonsgr]

According to the DS1216 datasheet:

Communication with the SmartWatch RAM is established by pattern recognition on a serial bit stream of 64 bits that must be matched by executing 64 consecutive write cycles containing the proper data on DQ0. On the SmartWatch ROM, communication with the clock is established using A2 and A0, and either OE or CE. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory. After the pattern match, the next 64 reads and/or writes are directed to the clock, and the RAM is disabled. Once the pattern is established, the next 64 read/write cycles will be directed to the RTC registers. When power is cycled, 64 reads should be executed prior to any writes to ensure that the RTC registers are not written. A pattern match is ignored if the RST bit is zero and the RST pin goes low during the match sequence. A pattern match is also terminated if a read occurs during the 64-bit match sequence.

and

Communication with the SmartWatch is established by pattern recognition of a serial bit stream of 64 bits that must be matched by executing 64 consecutive write cycles, placing address bit A2 low with the proper data on address bit A0.

So you need to read a byte from address #C000 in order to write a 0 and read a byte from #C001 to write a 1. You do 64 reads for the 64 bits of the recognition pattern.

Fully working smart watch routines have been published by @GUNHED here.
I tested them and work just fine with WinAPE emulator.
d_kef

Ok, but all these concern the "software" part of the process, my question is, from  "low level" hardware perspective, how can this "64 bits of the recognition pattern" is implemented? For example, after initial activation of time rom, do i have to "observe" 64 rom reads in a row and if all these reads match the recognition pattern, then what? Disable time rom, and enable the DS1216 "CS" to activate it? And for how long? Perhaps for the next 64 sequential memory access and then deactivate DS1216 again?
Sory if i insist in this matter, but since i was never involved with RTC and adding new chips in ULIfAC II board requires a lot of time & effort to get the 1st dev board for testing, i would like to be "as sure as it can be" at least with the hardware design.

[Pollo]

How the Dobbertin works is that you have to do 64 writes sequentially with the magic serial data in A0 to unlock the chip.
And then immediately do 64 reads sequentially to retrieve the 64 bits "packet" of time data in D0.
Then the chip locks itself and is again just a ROM.

[d_kef]

According to the DS1216 datasheet:

Communication with the SmartWatch RAM is established by pattern recognition on a serial bit stream of 64 bits that must be matched by executing 64 consecutive write cycles containing the proper data on DQ0. On the SmartWatch ROM, communication with the clock is established using A2 and A0, and either OE or CE. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory. After the pattern match, the next 64 reads and/or writes are directed to the clock, and the RAM is disabled. Once the pattern is established, the next 64 read/write cycles will be directed to the RTC registers. When power is cycled, 64 reads should be executed prior to any writes to ensure that the RTC registers are not written. A pattern match is ignored if the RST bit is zero and the RST pin goes low during the match sequence. A pattern match is also terminated if a read occurs during the 64-bit match sequence.

and

Communication with the SmartWatch is established by pattern recognition of a serial bit stream of 64 bits that must be matched by executing 64 consecutive write cycles, placing address bit A2 low with the proper data on address bit A0.

So you need to read a byte from address #C000 in order to write a 0 and read a byte from #C001 to write a 1. You do 64 reads for the 64 bits of the recognition pattern.

Fully working smart watch routines have been published by @GUNHED here.
I tested them and work just fine with WinAPE emulator.
d_kef

Ok, but all these concern the "software" part of the process, my question is, from  "low level" hardware perspective, how can this "64 bits of the recognition pattern" is implemented? For example, after initial activation of time rom, do i have to "observe" 64 rom reads in a row and if all these reads match the recognition pattern, then what? Disable time rom, and enable the DS1216 "CS" to activate it? And for how long? Perhaps for the next 64 sequential memory access and then deactivate DS1216 again?
Sory if i insist in this matter, but since i was never involved with RTC and adding new chips in ULIfAC II board requires a lot of time & effort to get the 1st dev board for testing, i would like to be "as sure as it can be" at least with the hardware design.

From the hardware point of view it is just another ROM. You treat it exactly like, for example, a 27C128 EPROM. The only difference is that you can also write to the RTC.

You cannot view this attachment.

d_kef

[Pollo]

And from an hardware point of view, you don't even need to care about the writes.
The Z80 will write to the RTC without performing a real write (POKE) operation.
Passing the magic data or writing to the RTC is all performed with PEEK and proper A2 and A0 signals.

That was the whole point of the device: you plug it on any ROM slot of any ROM board and voilà, you have an RTC.

[ikonsgr]

How the Dobbertin works is that you have to do 64 writes sequentially with the magic serial data in A0 to unlock the chip.
And then immediately do 64 reads sequentially to retrieve the 64 bits "packet" of time data in D0.
Then the chip locks itself and is again just a ROM.

And from an hardware point of view, you don't even need to care about the writes.
The Z80 will write to the RTC without performing a real write (POKE) operation.
Passing the magic data or writing to the RTC is all performed with PEEK and proper A2 and A0 signals.
That was the whole point of the device: you plug it on any ROM slot of any ROM board and voilà, you have an RTC.

If there is indeed an automatic deactivation of time chip upon 64 reads after activation (that need the specific 64 read pattern), that would make actual hardware design very easy!
 If i get it right, if you have time rom installed in different place (and not upon DS1216 adapter), then the only actual pins of DS1216 you need to connect (for the time chip to work right), are: power supply, A0,A2 and D0, no OE, CS, or WE are actually needed for the time chip communication! Is that right?
 If that's the case, then it would be very easy to add the DS1216 socket on ULIfAC II board (with only the above connections), and then i will need to develop the code on PIC mcu that will "deactivate" time rom (e.g. PIC MCU code will not return a byte from time rom upon rom reading) after receiving the 64 read pattern , and activate it again after 64 reads! 

[Pollo]

That I cannot confirm. Keep in mind I am not an electronician.
I see that the DS1315 time chip uses 16pins and they must be there for a reason.

What I am sure is that from the software side, you only communicate with it using PEEK and using A2, A0 and D0 (with the ROM mapped and at addresses corresponding to where the ROM is mapped).

[d_kef]

The /WE pin is there in case you want to mount a static RAM chip on top of the DS1216. According to the DS1216 datasheet this could be used as nonvolatile RAM. In our case it is irrelevant and should be tied (pulled-up) to 5V.
The only pins you need to drive is /CS and /OE and maybe you can have /CS permanently connected to GND and only use /OE. Or use /CS and connect /OE to Z80 /RD. A0, A2, D0 are normally connected to the CPC bus.

d_kef

[Pollo]

If i get it right, if you have time rom installed in different place (and not upon DS1216 adapter)

The time ROM needs to be on the same ROM slot as the time chip otherwise it won't work.