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#41
Muchas gracias, César!
#42
https://theretrohour.com/amstrad-cpc-40th-anniversary-with-roland-perry-pt-1-the-retro-hour-ep425/
Join us on a special journey back in time with Roland Perry, the visionary tech consultant behind the legendary Amstrad CPC, as we celebrate 40 incredible years of this iconic machine. In this not-to-be-missed episode, Roland takes us from his early days tinkering with electronics in school, through the founding of Ambit International, right up to his crucial role in steering the Amstrad CPC to success against heavyweights like the ZX Spectrum and Commodore 64.
Join us on a special journey back in time with Roland Perry, the visionary tech consultant behind the legendary Amstrad CPC, as we celebrate 40 incredible years of this iconic machine. In this not-to-be-missed episode, Roland takes us from his early days tinkering with electronics in school, through the founding of Ambit International, right up to his crucial role in steering the Amstrad CPC to success against heavyweights like the ZX Spectrum and Commodore 64.
#43
Code Select
bit 7 6 5 4 3 2 1 0
flag SF ZF YF HF XF PF NF CF
Bits 5 (YF) and 3 (XF) correspond to undocumented flags.
YF flag: A copy of bit 5 of the result.
XF flag: A copy of bit 3 of the result.
http://www.myquest.nl/z80undocumented/
It seems that in practice, on old NMOS Z80, they should follow this behavior pattern. But it is recommended not to base our programs on undocumented features because the current replacement 84C00 CMOS Z80 probably does not meet them.
#44
Copilot from Microsoft Edge say: 
The Flag Register (also known as the F register) in the Z80 processor is an 8-bit register that stores information about the results of the last operation performed. Each bit in the flag register represents a specific flag. Here is a description of each bit:
The Flag Register (also known as the F register) in the Z80 processor is an 8-bit register that stores information about the results of the last operation performed. Each bit in the flag register represents a specific flag. Here is a description of each bit:
- Bit 7 (S - Sign Flag): Set to 1 when the result of an operation is negative.
- Bit 6 (Z - Zero Flag): Set to 1 when the result of an operation is zero.
- Bit 5 (5 - Flag 5): A replica of the fifth bit of the accumulator (or result).
- Bit 4 (H - Half Carry Flag): Set to 1 when there is a half carry (or borrow) between bits 3 and 4 during addition or subtraction operations.
- Bit 3 (3 - Flag 3): A replica of the third bit of the accumulator (or result).
- Bit 2 (P/V - Parity/Overflow Flag): Set to 1 when the result of an operation has even parity (for logical operations) or when there is an overflow (for arithmetic operations).
- Bit 1 (N - Add/Subtract Flag): Set to 1 when the last operation was subtraction.
- Bit 0 (C - Carry Flag): Set to 1 when there is a carry (or borrow) from the most significant bit during addition or subtraction operations.
#45
im testing now 
#46
I ask about bits 3 and 5
#47
https://www.zilog.com/docs/z80/um0080.pdf
page 130 manual (144 pdf)
LDI
Condition Bits Affected
S is not affected.
Z is not affected.
H is reset.
P/V is set if BC – 1 ≠ 0; otherwise, it is reset.
N is reset.
C is not affected.
Table 21. Flag Register Bit Positions
Bit 7 6 5 4 3 2 1 0
Position S Z X H X P/V N C
X Not Used
page 130 manual (144 pdf)
LDI
Condition Bits Affected
S is not affected.
Z is not affected.
H is reset.
P/V is set if BC – 1 ≠ 0; otherwise, it is reset.
N is reset.
C is not affected.
Table 21. Flag Register Bit Positions
Bit 7 6 5 4 3 2 1 0
Position S Z X H X P/V N C
X Not Used
#48
Amstrad CPC hardware / Re: ULIfAC:Usb Mass storage,Wi...
Last post by linuxkostik64 - Yesterday at 19:18Hi John,
hi CPC folks,
With the CP2102 adapter, I was able to upgrade the firmware on my ULIfAC with the one that was uploaded to @ikonsgr's Dropbox a few days ago. I don't really know if the updated version is different from the one that was pre-installed on my ULIfAC when I got it in early April, but the upgrade worked fine according to the software. I connected Tx from the adapter to Tx from the ULIfAC and Rx to Rx. Apparently this was correct.
I'm absolutely delighted with the ULIfAC and can highly recommend thinking about buying it if someone is considering equipping a CPC with a Gotek and/or a RAM expansion or similar. I also think that such work needs to be supported.
Now I just hope that there will soon be a solution for Pinball Dreams and the memory problem associated with it, so that the game will also run with the ULIfAC.
Apart from that, I'm also thinking of buying an additional CPC 6128, but we'll see.
Thank you very much for your help and your friendly support!
Kind regards from Germany
Constantin
hi CPC folks,
With the CP2102 adapter, I was able to upgrade the firmware on my ULIfAC with the one that was uploaded to @ikonsgr's Dropbox a few days ago. I don't really know if the updated version is different from the one that was pre-installed on my ULIfAC when I got it in early April, but the upgrade worked fine according to the software. I connected Tx from the adapter to Tx from the ULIfAC and Rx to Rx. Apparently this was correct.
I'm absolutely delighted with the ULIfAC and can highly recommend thinking about buying it if someone is considering equipping a CPC with a Gotek and/or a RAM expansion or similar. I also think that such work needs to be supported.
Now I just hope that there will soon be a solution for Pinball Dreams and the memory problem associated with it, so that the game will also run with the ULIfAC. Apart from that, I'm also thinking of buying an additional CPC 6128, but we'll see.
Thank you very much for your help and your friendly support!
Kind regards from Germany
Constantin
#49
Hello
I noticed the bits 5 and 3 of register F changes on LDI and LDIR instructions, but I couldn't find a pattern of behaviour.
The only I was read about that bits is "The values of bits 7, 5 and 3 follow the values of the corresponding bits of the last 8 bit result of an instruction that changed the usual flags."
Does anybody know how they behave?
Thank you
I noticed the bits 5 and 3 of register F changes on LDI and LDIR instructions, but I couldn't find a pattern of behaviour.
The only I was read about that bits is "The values of bits 7, 5 and 3 follow the values of the corresponding bits of the last 8 bit result of an instruction that changed the usual flags."
Does anybody know how they behave?
Thank you
#50
Just went through the SMS one. It doesn't really go very deep but it's still well written and very interesting to read!