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Gate Array

3,314 bytes added, 30 May
correction of an error relating to IC
[[File:Amstrad 40007 Gate Array .png|right|thumb|Amstrad 40007 Gate Array]][[File:Amstrad 40010 Gate Array.png|right|thumb|Amstrad 40010 Gate Array]]
Also designated as Video gate Gate Array (VGA, not to be confused with the IBM PC compatible graphic card spec).
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In the [[KC Compact]] system, the functions of the Gate Array are "emulated" in TTL chips, [[CIO Overview|CIO]], and its color translation EPROM.
In the "cost-down" version of the CPC6128, the functions of the Gate Array are integrated into a an ASIC.
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== What does it do? ==
The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), bus arbitration, DRAM refresh, interrupt generation and memory arrangement.
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Every microsecond:
* The CRTC generates a memory address using it's MA and RA signal outputs. See the [[CRTC]] wiki page to know how the motherboard wiring transforms these signals into the Video Memory Address (VMA).
* The Gate Array fetches 2 bytes for each address. /CPU_ADDR is a 1MHz signal. So these 2 bytes are fetched sequentially. They are not interleaved with Z80 access. These bytes are fetched even when the border is on as this is required for DRAM refresh.
* The video hardware is given priority so that the display is not disrupted.
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== Interrupt generation DRAM refresh ==
Interrupts on the On Amstrad CPC are created by , the Gate Array based on settings from is responsible for the DRAM refresh, instead of using the CRTCZ80 built-in DRAM refresh mechanism. The Gate Array has an internal counter R52 (the R reason is for Raster) that counts from 0 to 51, incrementing after there can only be 3 DRAM accesses per microsecond on this architecture. Doing DRAM refresh on each HSYNC signalM1 cycle as it is done on MSX would bog down the CPU speed on CPC given its bus arbitration scheme.
On all CRTCs, R52 interrupts always start 1µs after the end The Z80 generates a maximum of an HSYNCone request per microsecond. But on CRTCs 3/4, HSYNCs occur 1µs later than on CRTCs 0/1/2. Which means that on CRTCs 3/4, interrupts start 1µs later than on CRTCs 0/1/2The CPC also requires two memory accesses per microsecond for reading video data.
R52 will return The CPC specs 4164-20 DRAMs. These require 330nS for a read or write cycle. The CPC also uses the optimised sequential CAS cycles to 0 and read the Gate Array will send an interrupt request on any of these conditionstwo video data bytes in half a microsecond. [https:* When it exceeds 51* By setting bit4 of the RMR register of the Gate Array to 1* At the end of the 2nd HSYNC after the start of //www.cpcwiki.eu/forum/amstrad-cpc-hardware/the VSYNC-cpc-revision-zero-article/msg243769/ Source]
When The way to cause the Gate Array sends an interrupt request:*If the interrupts were authorized at the time of the request, then bit5 of R52 RAM refresh to fail in both a Plus or normal CPC is cleared (but R52 was reset simply to 0 anyway) and stop a few bits of the interrupt takes place*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed CRTC address changing (the Gate Array then maintains its INT signal)ie. When interrupts are enabled (using never refresh the EI instructionselected area), bit5 of R52 is cleared and the interrupt takes place. This happens only '''after the instruction that follows EI''' as this Z80 instruction has a 1-instruction delay.
Note: On Amstrad PlusGenerally, only the interrupt management system is seriously beefed up. See Row address needs to be cycled, so stopping MA0 through MA7 from changing, and stopping the CPU from reading those rows, will cause data to be lost, quite quickly (generally around 4ms). [[ASIC]] wiki pagehttps://www.cpcwiki.eu/forum/amstrad-cpc-hardware/memory-refresh-plus/ Source]
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== CSYNC signal Interrupt generation ==[https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)]
The HSYNC and VSYNC signals are received from the [[CRTC]]. These signals CPU maskable interrupts are then modified generated by the Gate Array to C-HSYNC . This is done by using a 6bits internal counter and C-VSYNC monitoring the HSync and merged into a single CSYNC signal that will be sent to VSync signals produced by the displayCRTC.
When CRTC HSYNC is activeOn every falling edge of the HSync signal, the Gate Array immediately outputs will increment the palette colour blackcounter by one. If When the HSYNC is set to 14 characters then black counter reaches 52, the Gate Array raise the INT signal and reset the counter. With 50Hz PAL CRTC settings (one HSync every 64us) this will be output for 14µsproduce a 300Hz interrupt rate.
If a graphics mode change When the CPU acknowledge the interrupt (eg. it is pendinggoing to jump to the interrupt vector), the HSYNC pulse width needs to be at least 2µs for Gate Array to change will reset bit5 of the counter, so the graphics modenext interrupt can't occur closer than 32 HSync.
C-HSYNC begins 2µs after activation of When a VSync occurs, the CRTC HSYNC Gate Array will wait for two HSync and stays a maximum of 4µs (signal is cut short if HSYNC width is greater than 6).:
For example, if CRTC R2* If the counter>=4632 (bit5=1), then no interrupt request is issued and CRTC HSYNC width counter is 14 chars reset to 0.* If the counter<32 (bit5=0), then C-HSYNC starts at 48 an interrupt request is issued and lasts only until 51 includedcounter is reset to 0.
On Gate Array, even if the duration of the CRTC VSYNC This 2 HSync delay after a VSync is reduced used to 2 µsecondslet the main program, executed by the Gate Array will always output black CPU, enough time to sense the VSync (for 26 lines synchronisation with 4 lines of C-VSYNC to the monitor. While on ASIC/Pre-ASICdisplay, the CRTC VSYNC must be active as long as the C-VSYNC signal most likely) before an interrupt service routine is sent to the monitoreventually executed.
The Gate Array (and ASIC/Pre-ASIC) uses 2 internal counters to create its CSYNC signal:* H06 counts So all the number of CRTC characters processed during an HSYNC. H06 is incremented interrupt timings are mostly determined by the Gate Array for each CRTC character when CRTC HSYNC is activesettings. The Gate Array activates the C-HSYNC signal when H06 reaches 2Other than that, and changes its graphics mode if a change was pending. It deactivates this signal when H06 reaches 6.* V26 counts the number of HSYNCs occuring during a VSYNC. V26 is incremented internal interrupt counter can be cleared anytime by software using the Gate Array when the CRTC signals an end of HSYNC. The Gate Array activates the C-VSYNC signal when V26 reaches 2 (and if VSYNC is active on ASIC/Pre-ASIC). It deactivates this signal when V26 reaches 6. After the 26th line has been processed, the Gate Array stops outputting the palette colour blackRMR register.
If CRTC VSYNC is activated again while V26 is still in progressThe falling edge of the HSync trigger the counter, then V26 is reset to 0 and starts counting up again therefore modifying the HSYNC pulsesduration of the HSync with the CRTC Register 3 can delay the interrupt requests by a few microseconds.This can be used to adjust interrupt timings between CPC and Plus machines…
The HSYNC signal from Note: On Amstrad Plus, the CRTC interrupt management system is 0 when inactive and 1 when activeseriously beefed up. Same for VSYNCSee the [[ASIC]] wiki page.
C-HSYNC and C-VSYNC are composited using the XNOR function=== Timings ===[https://www. The resulting CSYNC signal produced by the Gate Array is 1 when inactive and 0 when activegrimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml#interrupt.generator Source: Grimware portal (Grim)]
On a CPC monitor, the CSYNC is rendered in "absolute black". It is darker than the palette colour black output The INT signal (active low) produced by the Gate Array. The electron beam , is basically turned offa short pulse of 1. Turning up 4us and starts right after the falling edge of the HSync signal (produced by the brightness level won't make it any brighterCRTC).
=== DI in peace ===[https://acpc.me/ACME/FANZINES Source: Amslive No4 (Madram)]  The GA maintains its int request until it is accepted.RST #38 occurs not after the EI, but after the instruction following the EI (the Z80 needs time to clean up its act). Even if the int isn't validated by the Z80, IC (interrupt counter) continues on its merry way.But after the EI, a test similar to the one seen for the VBL is performed: The interrupt is generated anyway, but:* If IC <br>32, IC is unchanged (the next int will then be produced 21 to 52 lines later).* Otherwise bit 5 of IC is set to zero.
== Controlling the Gate Array ==
The recommended I/O port address is &7Fxx.
 
The Gate Array is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. If you execute an I/O read operation on the Gate Array I/O address, the Gate Array will read an unpredictable value from the databus which will be in high-impedance state. If the value is a valid Gate Array command, it will be executed, otherwise nothing will happen. [https://www.grimware.org/doku.php/documentations/devices/gatearraydo=export_xhtml Source]
The function to be performed is selected by writing data to the Gate Array, the first bits of the data define the function selected (see table below). It is not possible to read from the Gate Array.
| 1 || 0 || 0 || style="text-align: center;" | n || All || RMR || Control Interrupt counter, ROM mapping and Graphics mode || Gate Array
|-
| rowspan="2"| 1 || rowspan="2"| 0 || rowspan="2"| 1 || style="text-align: center;" rowspan="2" | n || All || RMR || ''Ghost register'' || Gate Array (CPC) or locked ASIC (Plus)
|-
| 1 || 0 || 1 || style="text-align: center;" | n || Plus || RMR2 || ASIC & Advanced ROM mapping || Unlocked ASIC
|-
| 1 || 1 ||colspan=2 style="text-align: center;" | n || All || MMR || RAM memory mapping || PAL(only with 128KB or RAM expansion)
|}
In the CPC464, CPC664 and KC compact, MMR is performed in an external memory expansion (e.g. Dk'Tronics 64K RAM Expansion), if this expansion is not present then MMR is not available.
In the CPC6128, MMR is performed by a [[PAL16L8|PALchip]] located on the main PCB, or an external memory expansion.
In the 464+ and 6128+, MMR is performed by the ASIC or an external memory expansion. Please read the document on RAM management for more information.
==== ROM configuration selection ====
Bit 2 is used to enable or disable the lower ROM area. The lower ROM area occupies memory addresses &amp;0000-&amp;3fff and is used to access the operating system ROM. When the lower ROM area is is enabled, reading from &amp;0000-&amp;3FFF will return data in the ROM. When a value is written to &amp;0000-&amp;3FFF, it will be written to the RAM underneath the RAMROM. When it is disabled, data read from &amp;0000-&amp;3FFF will return the data in the RAM.
Similarly, bit 3 controls enabling or disabling of the upper ROM area. The upper ROM area occupies memory addressess &amp;C000-&amp;FFFF and is BASIC or any expansion ROMs which may be plugged into a ROM board/box. See the document on [[Upper ROM Bank Number|upper rom selection]] for more details. When the upper ROM area enabled, reading from &amp;c000-&amp;ffff, will return data in the ROM. When data is written to &amp;c000-&amp;FFFF, it will be written to the RAM at the same address as the ROM. When the upper ROM area is disabled, and data is read from &amp;c000-&amp;ffff it will be the data in the RAM.
Bit 4 controls the interrupt generation. It can be used to delay interrupts. See the document on interrupt generation for more information.
==== Summary ====
| 5 || 1
|-
| 4 || x || rowspan="2" |Lower ROM address and ASIC I/O page RMR addressing mode
|-
| 3 || x
|}
The lower {| class="wikitable"|+ RMR addressing modes!Bit 4!Bit 3!Lower ROM address and ![[Default I/O Port SummaryASIC|ASIC I/O page]] modes are:  |-Mode- ROM address ASIC I/O Page 00 |0|0|&0000-&3FFF |Disabled 01 |-|0|1|&4000-&7FFF |Disabled 10 |-|1|0|&8000-&BFFF |Disabled 11 |-|1|1|&0000-&3FFF |&4000-&7fff7FFF|}
The physical ROMs are also accessible as upper ROMs by using the [[Upper ROM Bank Number]] port and the RMR register.
=== Register MMR (RAM memory mapping) ===
This register exists only in CPCs with 128K RAM (like the CPC 6128), or CPCs equipped with [[Standard Memory Expansions]]).  Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip. See its wiki page.
{| class="wikitable"
!colspan=8|Displayed Pixels
!rowspan=2|Definition
!rowspan=2|Pixel clock
!rowspan=2|Default resolution
|-
!7
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 16 colorscolours|4 MHz|160x200, 20-column text
|-
|1
|colspan=2 style="text-align: center;"|D
|4 pixels in 4 colours
|8 MHz
|320x200, 40-column text
|-
|2
|G
|H
|8 pixels in 2 colorscolours|16 MHz|640x200, 80-column text
|-
|3
|colspan=4 style="text-align: center;"|A
|colspan=4 style="text-align: center;"|B
|2 pixels in 4 colorscolours|4 MHz|160x200, 20-column text
|}
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=== Palette sorted by Hardware Firmware Colour Numbers ===
The firmware colour palette is sorted by luminance value. {| class="FCK__ShowTableBorderswikitable"
|-
| ''Hardware Number||Firmware Number|| ''Colour Name''
| ''R&nbsp;%'' || ''G&nbsp;%'' || ''B&nbsp;%'' || ''ASIC'' || ''Colour''
|-
| 0 (40h) || 13 || White || 50|| 50|| 50|| #666|| bgcolor="#808080" | !Firmware Number!Hardware Number!Colour Name!R %!G %!B %!ASIC!Colour
|-
| 1 (41h) 0|| (13) 54h || White Black || 50 0|| 50 0|| 50 0|| #666000|| bgcolor="#808080000000" |
|-
| 2 1|| 44h (42hor 50h) || 19 || Sea Green Blue || 0||100 0|| 50|| #0F6006|| bgcolor="#00ff80000080" |
|-
| 3 (43h) 2|| 25 55h || Pastel Yellow Bright Blue ||100 0||100 0|| 50100|| #FF600F|| bgcolor="#ffff800000ff" |
|-
| 4 (44h) 3|| 1 5Ch || Blue Red || 50|| 0|| 0|| 50|| #006600|| bgcolor="#000080800000" |
|-
| 5 (45h) 4|| 7 58h || Purple Magenta ||10050|| 0|| 50|| #F06606|| bgcolor="#ff0080800080" |
|-
| 6 (46h) 5|| 10 5Dh || Cyan Mauve || 50|| 0|| 50|| 50100|| #06660F|| bgcolor="#0080808000ff" |
|-
| 7 (47h) 6|| 16 4Ch || Pink Bright Red ||100|| 50 0|| 50 0|| #F66F00|| bgcolor="#ff8080ff0000" |
|-
| 8 (48h) 7|| 45h (7or 48h) || Purple ||100|| 0|| 50|| #F06|| bgcolor="#ff0080" |
|-
| 9 (49h) 8|| (25) 4Dh || Pastel Yellow Bright Magenta ||100||100 0|| 50100|| #FF6F0F|| bgcolor="#ffff80ff00ff" |
|-
| 10 (4Ah) 9|| 24 56h || Bright Yellow Green ||100 0||10050|| 0|| #FF0060|| bgcolor="#ffff00008000" |
|-
| 11 (4Bh) 10|| 26 46h || Bright White Cyan ||100 0||10050||10050|| #FFF066|| bgcolor="#ffffff008080" |
|-
| 12 (4Ch) 11|| 6 57h || Bright Red ||100Sky Blue || 0|| 050||100|| #F0006F|| bgcolor="#ff00000080ff" |
|-
| 13 (4Dh) 12|| 8 5Eh || Bright MagentaYellow ||10050|| 050||100 0|| #F0F660|| bgcolor="#ff00ff808000" |
|-
| 14 13|| 40h (4Ehor 41h) || 15 White || Orange ||10050|| 50|| 050|| #F60666|| bgcolor="#ff8000808080" |
|-
| 15 (4Fh) 14|| 17 5Fh || Pastel MagentaBlue ||10050|| 50||100|| #F6F66F|| bgcolor="#ff80ff8080ff" |
|-
| 16 (50h) 15|| (1) 4Eh || Blue Orange || 0100|| 50|| 0|| 50|| #006F60|| bgcolor="#000080ff8000" |
|-
| 17 (51h) 16|| (19) 47h || Sea Green Pink || 0100||10050|| 50|| #0F6F66|| bgcolor="#00ff80ff8080" |
|-
| 18 (52h) 17|| 18 4Fh || Bright Green Pastel Magenta || 0100||10050|| 0100|| #0F0F6F|| bgcolor="#00ff00ff80ff" |
|-
| 19 (53h) 18|| 20 52h || Bright Cyan Green || 0||100||100 0|| #0FF0F0|| bgcolor="#00ffff00ff00" |
|-
| 20 19|| 42h (54hor 51h) || 0 || Black Sea Green || 0|| 0100|| 050|| #0000F6|| bgcolor="#00000000ff80" |
|-
| 21 (55h) 20|| 2 53h || Bright Blue Cyan || 0|| 0100||100|| #00F0FF|| bgcolor="#0000ff00ffff" |
|-
| 22 (56h) 21|| 9 5Ah || Green Lime || 050|| 50100|| 0|| #0606F0|| bgcolor="#00800080ff00" |
|-
| 23 (57h) 22|| 11 59h || Sky Blue || 0Pastel Green || 50||100|| 50|| #06F6F6|| bgcolor="#0080ff80ff80" |
|-
| 24 (58h) 23|| 4 5Bh || Magenta Pastel Cyan || 50|| 0100|| 50100|| #6066FF|| bgcolor="#80008080ffff" |
|-
| 25 (59h) 24|| 22 4Ah || Pastel Green Bright Yellow || 50100||100|| 50 0|| #6F6FF0|| bgcolor="#80ff80ffff00" |
|-
| 26 25|| 43h (5Ahor 49h) || 21 Pastel Yellow || Lime || 50100||100|| 050|| #6F0FF6|| bgcolor="#80ff00ffff80" |
|-
| 27 (5Bh) 26|| 23 4Bh || Pastel Cyan Bright White || 50||100||100|| #6FF|| bgcolor="#80ffff" | |-| 28 (5Ch) || 3 || Red || 50|| 0|| 0|| #600||bgcolor="#800000" | |-| 29 (5Dh) || 5 || Mauve || 50|| 0||100|| #60F||bgcolor="#8000ff" | |-| 30 (5Eh) || 12 || Yellow || 50|| 50|| 0|| #660||bgcolor="#808000" | |-| 31 (5Fh) || 14 || Pastel Blue || 50|| 50||100|| #66FFFF||bgcolor="#8080ffffffff" |
|}
 
Note: We can observe that the official Amstrad names of some colours are a bit silly: "red" is in fact brown, "yellow" is in fact khaki and "white" is in fact grey.
<br>
=== Palette sorted by Firmware Amstrad Colour Numbers Names ===
<gallery>Cpc 6128 master colour chat.jpg|Master colour chartCpc 6128 farbtabelle.jpg|FarbtabelleCpc 6128 palette des couleurs.jpg|Palette des couleursCpc 6128 tabla de colores.jpg|Tabla de colores</gallery> <br> === Palette sorted by Hardware Colour Numbers === {| class="FCK__ShowTableBorderswikitable"
|-
| ''Firmware Number'' || ''!Hardware Number'' || ''Colour Name'' | ''!Firmware Number!R&nbsp;%'' || ''!G&nbsp;%'' || ''!B&nbsp;%'' || ''!ASIC'' || ''!Colour''!Colour Name!German Name!French Name!Spanish Name
|-
| 0(40h) || 54h 13 ||Black 50|| 050|| 0|| 050|| #000666||bgcolor="#000000808080"||| White || Weiß || Blanc || Blanco
|-
| 1(41h) || 44h (or 50h13) ||Blue 50|| 0|| 050|| 50|| #006666||bgcolor="#000080808080"||| White || Weiß || Blanc || Blanco
|-
| 2(42h) || 55h ||Bright Blue 19 || 0|| 0100||10050|| #00F0F6||bgcolor="#0000ff00ff80"||| Sea Green || Seegrün || Vert marin || Verde marino
|-
| 3(43h) || 5Ch 25 ||Red 100|| 50100|| 0|| 050|| #600FF6||bgcolor="#800000ffff80"||| Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
| 4(44h) || 58h 1 ||Magenta || 50 0|| 0|| 50|| #606006||bgcolor="#800080000080"||| Blue || Blau || Bleu || Azul
|-
| 5(45h) || 5Dh 7 ||Mauve || 50100|| 0||10050|| #60FF06||bgcolor="#8000ffff0080"||| Purple || Purpur || Pourpre || Púrpura
|-
| 6(46h) || 4Ch ||Bright Red ||10010 || 0|| 050|| 50|| #F00066||bgcolor="#ff0000008080"||| Cyan || Blaugrün || Turquoise || Ciano
|-
| 7|| 45h (or 48h47h) ||Purple 16 ||100|| 050|| 50|| #F06F66||bgcolor="#ff0080ff8080"||| Pink || Rosa || Rose || Rosa
|-
| 8(48h) || 4Dh ||Bright Magenta (7) ||100|| 0||10050|| #F0FF06||bgcolor="#ff00ffff0080"||| Purple || Purpur || Pourpre || Púrpura
|-
| 9(49h) || 56h (25) ||Green 100|| 0100|| 50|| 0|| #060FF6||bgcolor="#008000ffff80"||| Pastel Yellow || Pastellgelb || Jaune pastel || Amarillo pastel
|-
|10(4Ah) || 46h 24 ||Cyan 100||100|| 0|| 50|| 50|| #066FF0||bgcolor="#008080ffff00"||| Bright Yellow || Hellgelb || Jaune vif || Amarillo brillante
|-
|11(4Bh) || 57h 26 ||Sky Blue 100|| 0|| 50100||100|| #06FFFF||bgcolor="#0080ffffffff"||| Bright White || Leuchtendweiß || Blanc brillant || Blanco brillante
|-
|12(4Ch) || 5Eh 6 ||Yellow 100|| 50|| 50 0|| 0|| #660F00||bgcolor="#808000ff0000"||| Bright Red || Hellrot || Rouge vif || Rojo brillante
|-
|13|| 40h (or 41h4Dh) ||White 8 || 50100|| 50 0|| 50100||#666F0F||bgcolor="#808080ff00ff"||| Bright Magenta|| helles Magenta || Magenta vif || Magenta brillante
|-
|14(4Eh) || 5Fh 15 ||Pastel Blue 100|| 50|| 50||100 0|| #66FF60||bgcolor="#8080ffff8000"||| Orange || Orange || Orange || Naranja
|-
|15(4Fh) || 4Eh ||Orange 17 ||100|| 50|| 0100|| #F60F6F|| bgcolor="#ff8000ff80ff"||| Pastel Magenta|| Pastell-magenta || Magenta pastel || Magenta pastel
|-
|16(50h) || 47h (1) ||Pink 0||100|| 50 0|| 50|| #F66006||bgcolor="#ff8080000080"||| Blue || Blau || Bleu || Azul
|-
|17(51h) || 4Fh (19) ||Pastel Magenta 0||100|| 50||100|| #F6F0F6||bgcolor="#ff80ff00ff80"||| Sea Green || Seegrün || Vert marin || Verde marino
|-
|18|| (52h ) ||Bright Green 18 || 0||100|| 0|| #0F0||bgcolor="#00ff00"||| Bright Green || Hellgrün || Vert vif || Verde brillante
|-
|19|| 42h (or 51h53h) ||Sea Green 20 || 0||100|| 50100|| #0F60FF||bgcolor="#00ff8000ffff"||| Bright Cyan || helles Blaugrün || Turquoise vif || Ciano brillante
|-
|20(54h) || 53h ||Bright Cyan 0 || 0||100 0||100 0|| #0FF000||bgcolor="#00ffff000000"||| Black || Schwarz || Noir || Negro
|-
|21(55h) || 5Ah 2 ||Lime 0|| 50 0||100|| 0|| #6F000F||bgcolor="#80ff000000ff"||| Bright Blue || Hellblau || Bleu vif || Azul brillante
|-
|22(56h) || 59h 9 ||Pastel Green 0|| 50||100|| 50 0|| #6F6060||bgcolor="#80ff80008000"||| Green || Grün || Vert || Verde
|-
|23(57h) || 5Bh 11 ||Pastel Cyan 0|| 50||100||100|| #6FF06F||bgcolor="#80ffff0080ff"||| Sky Blue || Himmelblau || Bleu ciel || Azul cielo
|-
|24(58h) || 4Ah 4 ||Bright Yellow ||100||10050|| 0|| 50|| #FF0606||bgcolor="#ffff00800080"||| Magenta || Magenta || Magenta || Magenta
|-
|25|| 43h (or 49h59h) ||Pastel Yellow 22 ||10050||100|| 50||#FF66F6||bgcolor="#ffff8080ff80"||| Pastel Green || Pastellgrün || Vert pastel || Verde pastel
|-
|26(5Ah) || 4Bh 21 || 50||100|| 0|| #6F0|| bgcolor="#80ff00" | || Lime ||Bright White Limonengrün || Vert citron || Verde lima|-| 27 (5Bh) || 23 || 50||100||100|| #6FF|| bgcolor="#80ffff" | || Pastel Cyan || Pastell-blaugrün|| Turquoise pastel|| Ciano pastel|-| 28 (5Ch) || 3 || 50|| 0|| 0|| #600|| bgcolor="#800000" | || Red || Rot || Rouge || Rojo|-| 29 (5Dh) || 5 || 50|| 0||100|| #FFF60F||bgcolor="#ffffff8000ff"||| Mauve || Hellviolett || Mauve || Malva|-| 30 (5Eh) || 12 || 50|| 50|| 0|| #660|| bgcolor="#808000" | || Yellow || Gelb || Jaune || Amarillo|-| 31 (5Fh) || 14 || 50|| 50||100|| #66F|| bgcolor="#8080ff" | || Pastel Blue || Pastellblau || Bleu pastel || Azul pastel
|}
The 0%, 50%, and 100% values in the above tables are "should-be" values. However, the real hardware doesn't exactly match that intensities. The actual intensities depend on the luminance mixing (R,G,B tied together via resistors), on chipset (classic CPC, or newer ASIC ones), and on the load applied by external hardware (Monitor, or TV set).
On an actual Amstrad CPC, the half-intensity colour signal is measured to be closer to 40% rather than the expected 50%. This was verified by [[Grim ]] and independently confirmed by [[Nocash]]. [https://www.grimware.org/doku.php/documentations/devices/gatearray#inkr Source]
* [[CPC Palette]] - some more details
This explains why the Amstrad engineers used these the following values to adapt the old colour palette to the new 12-bit palette on the Amstrad Plus:
* 0% became #0
* 50% became #6. They specifically chose #6 for the 50% value instead of the expected #7 or #8, to better match the real Amstrad CPC palette.
* 100% became #F
 
They specifically chose #6 for the 50% value instead of #7, to better match the real Amstrad CPC palette.
<br>
=== Green Screen Colours ===
On a green screen (, where all colours are shades of unsaturated green), the firmware colours (in BASIC colours) are in order of increasing intensity. Black is very darkdarkest green, and bright white is bright brightest green, and firmware colour 13 is a medium green. (Thanks to [[Mark Rison|Mark Rison]] for this information) The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. We have other values.
The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. Amstrad preferred to propose a completely different image system, not comparable to a conversion to monochrome, which would have limited the number of brightness levels to 21 (for example, colours 9 and 6 would have had the same luminance).
They opted for a table of 27 linear brightness steps. They assigned values of 1 (1kΩ) for blue, 3 (3.3kΩ) for red, and 9 (10kΩ) for green.
<br> ==== To calculate the luminance value ====
'''Red'''
*0% =&gt; do not add anything  *50% =&gt; add 3  *100% =&gt; add 6
'''Green'''
*0% =&gt; do not add anything  *50% =&gt; add 9  *100% =&gt; add 18
'''Blue'''
*0% =&gt; do not add anything  *50% =&gt; add 1  *100% =&gt; add 2
<br>
[[File:Ga.pinout.40007.png]] [[File:Ga.pinout.40008.40010.png]]
 
Note: Some CPC motherboards can accommodate both types of Gate Array pinouts. [https://thecheshirec.at/2024/10/06/il-existe-une-carte-multi-gate-array-et-cest-amstrad-qui-la-faite/ Source]
<br>
== External links ==
*[https://bread80.com/2021/06/03/understanding-the-amstrad-cpc-video-ram-and-gate-array-subsystem/ Electronic signals analysis of the Gate Array by Bread80]
* [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf Gate Array documentation in Amstrad CRTC Compendium]
* [https://www.grimware.org/doku.php/documentations/devices/gatearray Gate Array documentation from Grimware]
* [http://quasar.cpcscene.net/doku.php?id=assem:gate_array Quasar Gate Array documentation (in french)]
*[[Gate Array and ASIC Pin-Outs]]
 *[[Video modesPAL16L8]] : for other informations on colours and pixels. *[[CRTC]] : the other video stuff.RAM arrangement
*[[ASIC]] : for Plus users
*[[CRTC]] : the other video stuff
*[[Synchronising with the CRTC and display]] : technical details on the relationship between Gate Array and CRTC.
 
*[[Video modes]] : for other informations on colours and pixels.
*[[Media:40010-simplified V03.pdf]] [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/gate-array-decapped!/msg170713/#msg170713 Forum thread] Gate Array schematics - reverse engineered by Gerald
[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]][[Category:CPC Internal Components]][[Category:Electronic Component]]
Longshot
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