Changes
/* Gate Array Register 3 */
Writing to port #7Fxx with bit 7 and bit 6 of data set to 1 can be used to set page 3 RAM bank in Aleste mapper mode, or to define CPC RAM configuration in CPC mode.
See also: [[Standard Memory Expansions]]. '''Actually''', it seems to work more like an Inicron expansion (which isn't fully compatible with the dk'tronics standard).
== Upper ROM Bank ==
