Z80

Zilog Z80A

The Z80 is an 8-bit microprocessor designed by Zilog founder and CEO Federico Faggin. It is a successor of the Intel 8080, also designed by Federico Faggin. First released in July 1976, this CPU is used in the Amstrad CPC / Plus / PCW computers.

The Z80/Z80A was a very popular microprocessor, used in a wide range of applications, from gaming consoles like the ColecoVision, the Sega Master System and Sega GameGear to personal computers like the ZX81, ZX Spectrum and MSX.

It was used in the Commodore C128 as a secondary processor in order to achieve CP/M compatibility. Similarly, the Acorn Z80 Second Processor expansion for the BBC Micro enabled CP/M compatibility. And the popular Z-80 SoftCard expansion did the same for the Apple II.

The best-selling devices to feature a Zilog Z80 are the Sega MegaDrive with 40 million units sold Source, and the TI graphing calculators with 90 million units sold Source.

Although there were definitely other CPUs in use in the 1980s, the vast majority of microcomputers people had at home or at the office used either a MOS 6502 (or one of its variants), a Zilog Z80, an early member of the Intel 8086 family, or a Motorola 68000.

In the early 1970s, Intel developed the 8080, one of the first widely used microprocessors. However, a group of engineers led by Federico Faggin, the originator of the 8080 architecture in early 1972, left Intel to start their own company called Zilog in 1974.

At Zilog, Faggin and his team wanted to create an improved version of the Intel 8080 that would be more efficient, flexible, and easier to use. This led to the development of the Z80, which was designed to be both backward-compatible with the 8080 and more powerful. This compatibility meant that any software written for the 8080 could run on the Z80, making it an attractive upgrade for manufacturers and developers.

The Z80 had several key improvements over the 8080. It featured more registers, block instructions, bitwise ops, indexed addressing, and improved interrupt handling. It also had built-in memory refresh for dynamic RAM, that made it easier to build systems around it.

The Z80 microprocessor is an 8-bit CPU with a 4-bit ALU and a 16-bit address bus capable of direct access to 64KB of memory space. The Z80 is a little-endian CPU, meaning it stores 16-bit values with the least significant byte first, followed by the most significant byte.

It has a language of 252 root instructions and with the reserved 4 bytes as prefixes, access to an additional 308 instructions. Although it lacks the raw processing power of processors like the Intel 80x86 or the Motorola 68000 series, the Z80 is extremely useful for low cost control applications.

The Z80 has about 8500 transistors. To put it into perspective, 64KB of DRAM contains 524288 transistors, as 1 bit of DRAM needs 1 transistor. Fun fact: an Amstrad CPC equipped with a 4MB RAM expansion has 32 million transistors dedicated to RAM while the Z80 CPU still has only 8500 transistors.

The Z80 is mid-1970s technology while the 64KB DRAM is early-1980s technology and the 4MB DRAM is early-1990s technology.

The Z80 comes in a 40-pin DIP package. It has been manufactured in A, B, and C models, differing only in maximum clock speed. It also has been manufactured as a stand-alone microcontroller with various configurations of on-chip RAM and EPROM.

While the ALU is responsible for most flag changes, other instructions like stack operations (POP AF), specific register loads (LD A,I/R), direct flag commands (SCF, CCF), bit tests (BIT), and the control logic within block instructions also modify the flag register.

 On Zilog NMOS Z80, when the instruction doesn't compute new flags, this register is cleared instead. But not on NEC NMOS Z80. And CMOS Z80 behave in a different way too.
 Normally, you never see the content of this register. But it leaks through F5 and F3 in the SCF/CCF instructions. Source
 Only 1 extra bit (F-changed) is needed for emulation Source. Also note that while POP AF and EX AF,AF' modify F, they do not compute new flag values. Source

Notes:

• EIP and IMP can be fusioned into a 3-bit internal state as there are only 7 possible values for the prefixes (none, ed, dd, fd, cb, ddcb, fdcb). Probably not a win though as it makes everything more confusing.
• IFF1 / IFF2 are called IEF1 / IEF2 (Interrupt Enable Flip-flops) in the Zilog eZ80 manual.

Many instructions, such as arithmetic instructions or loads, include more than one operand. In these cases, two different types of addressing can be employed in the same instruction.

For example, LD (HL),42 uses Immediate Addressing to specify the source and Register Indirect Addressing to specify the destination, to perform the operation: M(HL) ← 42.

For an instruction to fully execute, the Z80 goes through these key phases in order:

1. Prefix and Opcode Fetch (M1)
2. Operand Fetch (if needed)
3. Memory Read / I/O Read (if needed)
4. Operation
5. Memory Write / I/O Write (if needed)
6. At the end of every instruction, the IRQ (if IFF1 is active) and NMI pins are checked
7. Loop (for block instructions only)

For example, the instruction RL (IX+42) will execute as follow:

1. M1 (4 t-states): Prefix fetch &DD then increment PC
2. M1 (4 t-states): Opcode fetch &CB (the second prefix) then increment PC
3. M2 (3 t-states): Operand fetch 42 (the displacement byte) then increment PC
4. M3 (5 t-states): Operand fetch &16 (the real opcode) then increment PC, while calculating the address IX+42
5. M4 (4 t-states): Memory read at address IX+42 then RL operation
6. M5 (3 t-states): Memory write at address IX+42

Legend

Flags

• - = no change
• + = change by definition (if noted, by the operation marked with '=> flags', otherwise by the only non-single-bit operation):

* S = sign, bit 7 of the result byte (accumulator or high byte for 16-bit operations)
* Z = zero, set if the result is zero (8 or 16-bit value)
* 5 = undocumented, bit 5 of the result byte
* H = half-carry, the carry (theoretical bit 4) of the low nibble of the result byte
* 3 = undocumented, bit 3 of the result byte
* P = parity (set if the result byte has an even number of bits set) or overflow (set when crossing the boundary of the signed range); always specified
* N = negative, set if the previous operation was a subtraction; always specified
* C = carry, the theoretical bit 8 of the result byte

• 0 = always reset
• 1 = always set
• X = change described under effect
• P = parity (only for the parity flag)
• V = overflow (only for the parity flag)
• A = OR with the respective bit of the accumulator
• C = set if the counter (bc) is nonzero after decrementing

Registers

• r,r̃: 000=B, 001=C, 010=D, 011=E, 100=H, 101=L, 111=A (110 is treated separately)
• s,s̃: 000=B, 001=C, 010=D, 011=E, 100=IXH/IYH, 101=IXL/IYL, 111=A (110 is treated separately)
• pp: 00=BC, 01=DE, 10=HL, 11=SP
• p̃p̃: 00=BC, 01=DE, 10=HL, 11=AF
• qq: 00=BC, 01=DE, 10=IX/IY, 11=SP
• q̃q̃: 00=BC, 01=DE, 10=IX/IY, 11=AF

Miscellaneous

• () = indirection
• (()) = I/O port
• [] = operator precedence (to avoid confusion with indirection)
• e.b = the bth bit of the value of expression e
• * = any bit value (0 or 1)
• wz = an internal 16-bit register connected to 16-bit operations
• tmp, tmp2 = temporary storage whose value is thrown away after each instruction

M-Cycle Sequences have been deduced logically and verified on real hardware. See Arduino Z80 dongle bus activity dump.

Load group

16-bit Arithmetic group

8-bit ALU group

Note: Arithmetic operations ADD, ADC, SUB, SBC, CP calculate flags in the same way. Logic operations AND, XOR, OR calculate flags in the same way.

Note2: INC/DEC are meant to be used for loops and counters. They don't modify CF, to allow loops and counters to increment/decrement without disturbing carry-sensitive logic.

BCD group

if hf or [a and 0x0f > 9] then tmp -= 0x06
if cf or [a > 0x99] then tmp -= 0x60

if hf or [a and 0x0f > 9] then tmp += 0x06
if cf or [a > 0x99] then tmp += 0x60

ROT group

Note: All ROT operations calculate flags in the same way, except for 8080-style ROT operations (RLCA, RRCA, RLA, RRA).

Bitwise group

Block group

Note: The INI instruction has incorrect timing in the official Zilog manual Source.

I/O group

Control flow group

CPU control group

In the Z80, M-cycles represent high-level execution cycles for an instruction, while T-states are individual clock cycles. Each M-cycle consists of several T-states, and instructions require one or more M-cycles.

M-cycles can be classified as follows:

• Opcode Fetch (aka M1 cycle): this is always the first (and sometimes only) machine cycle in an instruction (4 T-states)
• Memory Read: read a byte from memory (3 T-states)
• Memory Write: write a byte to memory (3 T-states)
• IO Read: read a byte from an IO port (4 T-states)
• IO Write: write a byte to an IO port (4 T-states)
• Interrupt Acknowledge: special M-cycle which is executed at the start of maskable interrupt handling
• Extra: many instructions contain extra T-states necessary for computations. In the official CPU documentation, these are sometimes identified as a separate M-cycle, and sometimes just lumped together with other M-cycle types. For example:
  • The INC pp instruction has only one M-cycle, but consisting of 6 T-states instead of the usual 4.
  • The instruction RST t has an M1 cycle consisting of 5 T-states instead of the usual 4.
  • The CALL cc,nn instruction has an extra T-state inserted in M3 depending if cc is true or not.

Every place the Z80 manual shows a memory read taking more than 3 clocks, or an opcode fetch/decode taking more than 4 clocks, it should be interpreted as "standard read or fetch cycle with (n - 3) or (n - 4) internal operations after". Source

Note: 0=Active, 1=Inactive, Z=High Impedance

Timing Diagrams

• 

  Basic CPU Timing

• 

  Opcode Fetch

• 

  Memory Read or Write

• 

  Input or Output

• 

  Interrupt Request

• 

  NMI Request

• 

  Bus Request

• 

  HALT Exit

Opcode fetches are compressed into just 2 clocks; the second 2 clocks of an M1 cycle are DRAM refresh, in which the Z80 puts the contents of the R register on the address bus and then increments the lower 7 bits of R.

Since opcode fetches require the memory to respond faster than normal read/write cycles do, some machines (like the MSX) have an externally-inserted wait state only on M1 cycles. Source

CPC Timings

On MSX, bus arbitration only applies to M1 machine cycles but access to VRAM has other limitations. On ZX Spectrum, bus arbitration is done not by using the /WAIT pin but by disabling the CPU clock when needed.

On CPC, bus arbitration occurs on every CPU bus access. The Gate Array asserts the /WAIT pin on the Z80 for 3 out of every 4 cycles, effectively aligning all bus operations to a 4-tick cycle. The Z80 extends T2 indefinitely by adding wait states until /WAIT is released.

The NOPs column corresponds to CPC timings, which account for the bus arbitration. The NOP instruction takes 4 cycles. This is the minimum amount of cycles an instruction can take.

Every M-cycle that involves a memory or I/O access will stretch the previous M-cycle due to bus arbitration. But beware, some M-cycles are purely internal and don't involve a memory or I/O access. So those won't stretch the previous M-cycle.

Nevertheless, a few CPC timings can appear surprising at first glance:

• Instructions LD (IX+d),r and LD (IX+d),n take 5 and 6 NOPs respectively, even though they are both listed as 19 (4,4,3,5,3) cycles in the datasheet. This happens because LD (IX+d),r has one less memory access operation to do compared to LD (IX+d),n as it does not have to fetch its operand from memory.

• Instructions IN r,(C) and OUT (C),r take 4 NOPs with CPC timings, even though they are listed as 12 (4,4,4) cycles in the datasheet. This happens because I/O access is not aligned with memory access. On Zilog manual, it is precised that one wait-state TW is automatically inserted after T2 on I/O access.

The CPC timings of some instructions will be altered if an interrupt happens. The interrupt test occurs on the last T-state of the instruction, and if it's low, the Z80 will insert 2 wait states to acknowledge the interrupt.

So, instructions which end in the third or fourth T-state relative to the read alignment for the next instruction fetch will be delayed by an extra 4 T-states. The few instructions which end in the first or second T-state won't since the first instruction fetch/read in the interrupt won't be delayed an extra 4 T-states. Source

The Z80 follows a 2-3-3 opcode bit pattern. Register instructions normally use three bits to specify the register used: 000=B, 001=C, 010=D, 011=E, 100=H, 101=L, 110=indirect through HL, 111=A.

Register pairs are encoded as: 00=BC, 01=DE, 10=HL, 11=SP. The PUSH and POP instructions use a slightly different encoding: 00=BC, 01=DE, 10=HL, 11=AF.

Three bits are used to specify condition codes: 000=NZ (Non Zero), 001=Z (Zero), 010=NC (Non Carry), 011=C (Carry), 100=PO (Parity Odd), 101=PE (Parity Even), 110=P (Plus), 111=M (Minus). The JR instruction only decodes the 2 lower bits of the condition code.

Condition C (carry) is unrecognizable from register C. To recognize which it is, conditions (flags) are used only in instructions: CALL, JR, JP, RET.

All CB-prefixed opcodes and half of the standard opcodes (from &40 to &BF) follow a strict uniform layout. The sole exception is the HALT instruction (opcode &76), which replaces the expected LD (HL),(HL) instruction.

The rest of the opcode table is also neatly organised but in a horizontal way instead of vertical.

Any instruction in bold is undocumented by Zilog.

Standard opcodes

CB-prefixed opcodes

ED-prefixed opcodes

The opcodes that are not mentioned in the following table are EDNOP (ED-prefixed NOP instruction). Thay have no effect but take 8 cycles and increment the register R two times. EDED, EDDD, EDFD and EDCB are also EDNOP instructions.

Notes:

• The opcode ED70 reads the port indicated by the register C without keeping the result, but it modifies the register F
• The opcode ED71 is used in many PSG players/drivers, as it's very useful for the PSG access, which sits behind the PPI. But beware, on a CMOS Z80 this opcode behaves differently. It corresponds to the instruction OUT (C),#FF instead Source
• The opcode EDFF is used by Winape (and other emulators) to break into the debugger (a 'break opcode') Source

DD or FD-prefixed opcodes

If an opcode is prefixed by DD, the instruction is changed as follows:

• HL is replaced by IX
• H is replaced by IXH
• L is replaced by IXL
• (HL) is replaced by (IX+d)

Same for the FD prefix but with IY instead of IX.

There are 3 exceptions:

• In the instruction EX DE,HL, HL will not be replaced with IX or IY. The EXX instruction is not affected either.
• If (HL) and L or H are used in the same instruction, L and H are not replaced with IXL or IXH. For instance LD L,(IX+d) stores the content of (IX+d) into L, not IXL.
• DD, ED or FD prefixes cancel the effects of immediately preceding DD or FD prefixes (those become NONI: No Op No Interrupt). In other words, ED-prefixed opcodes cannot be altered by DD or FD prefixes.

DDCB or FDCB-prefixed opcodes

When a DD or FD prefix is followed by a CB byte, the CB acts as a second prefix. A mandatory displacement byte comes next, and then the actual opcode.

If the instruction produces output other than in the flags (i.e. all except BIT), then the result gets placed both into (IX+d) or (IY+d) and into the register one would normally expect to be altered.

DDCB and FDCB-prefixed instructions only increment the R register twice. Source

• RLA, RRA, RLCA, RRCA are essentially optimized versions, one byte smaller and one M-cycle faster, of RL A, RR A, RLC A, RRC A.
• ADD A,A is one byte smaller and one M-cycle faster than SLA A.
• Similarly, ADD HL,HL is 3 bytes smaller and one M-cycle faster than SLA L; RL H.
• DJNZ loop is one byte smaller and is as fast as DEC B; JR nz,loop on CPC.
• For a smaller conditional RST #38, use JR cc,-1. This will cause a conditional jump to the displacement byte (#FF) which is the RST #38 opcode.
• To quickly invert all bits of A, CPL is one byte shorter and one M-cycle faster than XOR #FF.
• To set A to zero, XOR A is one byte smaller and one M-cycle faster than LD A,0.
• To check if A is zero, AND A or OR A are one byte smaller and one M-cycle faster than CP 0.
• An unrolled LDI loop is faster than LDIR. The same applies to other Z80 block instructions.
• If tables are aligned to a 256-byte boundary, the contents can be accessed by placing the index in a register such as L and the table address in H. This is faster than loading the full unaligned 16-bit address and adding a 16-bit index to it, and makes accessing tables with a size of 256 bytes or less very convenient.

• RETI and RETN are identical instructions Source. The only reason for RETI is so that some other hardware can detect the specific case of returning from the interrupt, by detecting the RETI opcode on the data bus.
• EI has a 1-instruction delay. It is necessary for doing EI/RETI without any danger of nested interrupt routines.
• At the end of an NMI service routine, the earliest moment a maskable interrupt will be triggered is at the end of the instruction following RETN. Source
• RST instructions are just a CALL instruction to a fixed address baked in the instruction itself.
• Unlike the conditional JP, CALL, RET instructions which have access to all conditions, JR is limited to NZ, Z, NC, C conditions.
• Despite what the syntax of the instructions JP (HL/IX/IY) suggests, PC will be loaded with the contents of the register itself, not the indexed value. Those instructions should be understood as JP HL/IX/IY.
• The instructions LD A,A, LD B,B, LD C,C, LD D,D, LD E,E, LD H,H and LD L,L are useless. Their existence is just a side effect of how instructions are encoded as opcodes in the CPU.
• The instructions LD (nn),HL and LD HL,(nn) exist both as standard opcodes and ED-prefixed opcodes.
• The 16-bit instructions ADD HL,ss, ADC HL,ss and SBC HL,ss exist but not the instruction SUB HL,ss.
• While the syntax of the 8-bit ADD, ADC and SBC instructions all explicitly mention the A register, the SUB instruction does not mention it. On the Zilog eZ80, the SUB instruction explicitly mention the A register.
• The Z80 has a lot of 8-bit registers but it can only really do arithmetic on the A register.
• The IN r,(C) instruction updates flags but IN A,(n) does not.
• IN r,(C) and OUT (C),r instructions syntax is misleading as these instructions actually use the full 16-bit port address contained in BC. On the Zilog eZ80, these instructions are correctly named IN, r,(BC) and OUT (BC),r.
• The Amstrad engineers chose to use the high byte of the address (register B) for chip selection instead of the low byte (register C) in I/O operations. As a result, OTIR / OTDR / INIR / INDR instructions cannot be used on Amstrad CPC for transferring or reading a sequence of values on a port, as these instructions use the B register as a counter.
• INI/IND/INIR/INDR decrease B after storing the byte from the hardware port into memory. And OUTI/OUTD/OTIR/OTDR decrease B before sending the memory byte to the hardware port. Source
• All PUSH and POP instructions utilize a 16-bit operand and the high-order byte is always pushed first and popped last. PUSH HL is PUSH H then L. POP HL is POP L then H.
• When an LDxR / CPxR / INxR / OTxR instruction is interrupted, the interrupt handler sees some flags in a different state. Source
• LD A,I and LD A,R normally copy the state of IFF2 to the Parity flag. NMOS Z80 suffers a problem whereby LD A,I and LD A,R record the state of IFF2 after it has been reset if an interrupt is delivered during that instruction. Source
• Although not mentioned in Zilog documentation, the Z80 CPU supports two types of reset: normal and special. A normal reset disables the maskable interrupt, selects interrupt mode 0, zeroes registers I & R and zeroes the program counter (PC). A special reset zeroes PC only. Furthermore, a hardware bug was discovered when the special reset occurs after a HALT instruction. Source
• Almost all Z80 inputs are sampled on a rising clock, but the /WAIT signal is sampled on a falling clock. Source

• The 6502’s Decimal (BCD) mode automatically adjusts ADC and SBC results, while the Z80 requires a DAA instruction after each BCD addition and subtraction.
• The 6502 uses only one addressing mode per instruction, while the Z80 can combine two different addressing modes within a single instruction.
• The 6502 post-decrements on PHA and pre-increments on PLA, while the Z80 pre-decrements on PUSH and post-increments on POP.
• The 6502 saves flags automatically during interrupts; while the Z80 requires PUSH AF and POP AF.
• The 6502 only updates flags that are directly relevant to the operation's result. For example, EOR doesn't conceptually involve a carry, so the Carry flag is left untouched. On the Z80, XOR always clears the Carry flag to ensure a clean flag state.

The ALU uses two temporary registers that are not directly visible to the programmer:

• The Accumulator Temporary register (ACT) holds the accumulator value while an ALU operation is performed. This allows the accumulator to be updated with the new value without causing a race condition.
• The second temporary register (TMP) holds the other argument for the ALU operation. The TMP register typically holds a value from memory or another register.

See: How the Z80's registers are implemented The 16-bit increment/decrement circuit The 4-bit ALU Z80 die-shot (zeptobars) Z80 die-shot (bercovici)

The Z80 is based around a more complicated structure than the 6502. Here the instruction is sent through a (rather) simple decoder. The decoder is built from a PLA. Simple because 8080/Z80 code offer fewer variants (i.e. addressing modes) and is quite regular compared with a 6502. The decoder creates multiple lines for each instruction or instruction group, which are fed into the second stage.

Two counters are set up in parallel. One counting the Memory (or Machine) states (M1..M5), the other Time states (T1..T5) within (note1). With a new instruction the M counter gets reset to 1, with each M state the T counter gets reset.

The second stage of instruction decode is something that is much like another PLA, but built out of single gates (note2). The gates are set up much like a grid with the timing signals (M1..M5 & T1..T5) as horizontal input and the PLA output (instructions/instruction groups) as vertical input. The gate is built along the vertical line and combining its signal with one or more timing signals using AND/NOR logic (note3). The output of these gates are fed into the discrete logic of the execution units. Source

• note1: this internal structure is also the reason for this otherwise unusual notation used throughout all Z80 documentation.

• note2: The structure is quite similar to a gate array - except that only needed inputs/functions are cast into silicon.

• note3: CMOS offers the feature to build rather complex gates with multiple inputs in a simple way - to some extend this is maybe the most unique feature about the Z80 design.

See: ARM1, Z80, 6502 instruction sequencing compared Z80 instruction decode PLA table Script processing the PLA table

• RFSH = outputs a signal to allow for memory to be refreshed
• M1 = Z80 is fetching next instruction from memory
• RESET = used to reset the Z80
• BUSRQ = Bus Request (used by external devices to request control)
• WAIT = makes the the Z80 wait during a read or write operation
• BUSACK = Bus Acknowledge – signals when Z80 is ready to hand over control
• WR = signals a memory or I/O write operation
• RD = signals a memory or I/O read operation
• INT = hardware interrupt occurred
• NMI = Non Maskable Interrupt (higher priority than the INT)
• HALT = Z80 is in a halted state
• MREQ = Z80 wants to access memory
• IORQ = Z80 wants to access an I/O port

See: Why Z80's data pins are scrambled

IC Models used in CPC

The Z80 CPU has been manufactured by others, and various Z80s have been used in the construction of the CPC during its lifetime:

• Mostek MK3880N-4 Source
• NEC D780C Source
• SGS Z8400AB1 Source
• ST Z8400AB1 Source
• Zilog Z8400APS Source
• Zilog Z0840004PSC Source

All the Z80 CPUs that Amstrad used on CPC and Plus machines are NMOS. Source

Modern incarnations

Zilog ended the production of the Z80 in April 2024. This chip is still available in ample quantities through NOS chip suppliers and can be purchased for 1.20€. Source

Zilog continues to produce the eZ80 processor, a binary-compatible upgrade of the Z80, which runs at up to 50MHz but performs like a 150MHz Z80 due to being 3 times faster at the same clock speed.

Emulation

Apart from surplus/new Z80-clones that are quite easy to find, many emulations depend on software implementations of the Z80:

• libZ80 Ultra accurate ANSI C implementation
• arnold uses InkZ80, written in C++ (taken from the InkSpector ZX Spectrum emulator)
• A-Z80 Ultra accurate Verilog implementation A-Z80 Timing Table

Other Variants

The GBZ80 (Sharp SM83) that powers the original Nintendo Gameboy and Gameboy Color is kind of an in-between the Intel 8080 and Z80. GBZ80 opcodes

The Sega Mega Drive, Master System and Game Gear use a standard Z80 CPU. Genesis sound software manual Master System reference manual Game Gear reference manual

The KC Compact uses the U880, which is an unlicensed clone of the Z80 manufactured by MME. It was the most widely used microprocessor in the German Democratic Republic. Source

The КМ1582ВМ is a Soviet clone of the Z80. It is used in the Aleste 520EX clone of the Amstrad CPC computer.

The ASCII R800 that powers the MSX TurboR is a seriously beefed up version of the Z80:

• The ALU of the R800 is 16-bit instead of 4-bit for the Z80. This change allows instructions that were being executed in 4 cycles to be done in 1 cycle.

• The instruction set of the R800 is almost identical to the Z80. Only 2 instructions have been added: MULUB and MULUW. And many of the undocumented instructions of the Z80 were made official.

• Z80 Family Databook Z80 CPU Peripherals
• Zilog Z80 User Manual (2016)
• Zilog Z80 Technical Manual
• Mostek Z80 Programming Manual
• Mostek Z80 Technical Manual Text version - provides a detailed breakdown of the machine cycles
• Mostek Z80 Micro-Reference Manual
• Media:Z80 CPU Instant Reference Card (Color).pdf
• Media:Z80 CPC Timings cheat sheet.20230709.pdf
• Rodnay Zaks Programming the Z80 Z80 Hardware Organization
• ZX-PK forum topic on reverse engineering the Z80 (RU)
• MEMPTR, esoteric register of the Z80 CPU inir/indr/otir/otdr instructions and MEMPTR
• Z80 - undocumented opcodes
• Instruction List with T-States

• Z80 at the English-language Wikipedia
• Zilog Company's website
• Home of the Z80 CPU
• Zilog Z80 oral history panel
• Z80 article on Sinclair Wiki
• Learn Assembly Programming with ChibiAkumas Multi-platform Z80 tutorial
• Z80 documentation from Grimware
• Interrupt behaviour of the Z80 CPU
• Behaviour of the undocumented flags
• Zilog Z80 instruction set
• Z80 CPU instruction set database
• Decoding Z80 opcodes
• Z80 Explorer
• VisualZ80remix Detailed look at Z80 instruction timings with the help of a Z80 netlist simulation
• Cycle-stepped Z80 emulation how-to Internal Z80 behaviour described in Yaml format
• Tom Harte's SingleStepTests