Besides the Amstrad CPC, this chip equipped the [[PCW|Amstrad PCW]], the [[ZX Spectrum|ZX Spectrum +3]] and the [[PC|IBM PC]] (including [[Amstrad PC]]).
The recommended ports used by Amstrad and compatible interfaces are:
{| class="wikitable"
|-
!I/O port address
!Function
|-
|&FA7E||Floppy Motor On/Off Flipflop
|-
|&FB7E||FDC 765 Main Status Register (read only)
|-
|&FB7F||FDC 765 Data Register (read/write)
|}
Bit b10 of the address port is reset as the FDC is seen as an expansion, even if it is an internal chip. Bit b7 is reset to select the FDC. Bits b8 and b0 are used to select the specific mode of operation. All other bits should be set to 1 to avoid conflict. [https://www.cpc-power.com/cpcarchives/index.php?page=articles&num=48 Source]
The [[Vortex Disc Drives|Vortex disc interface]] uses other ports. See its dedicated wiki page.
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== Accessing the FDC 765 ==
The recommended ports used by Amstrad and compatible interfaces are: {| class="wikitable"|-!I/O port address!Function|-|&FA7E||Floppy Motor On/Off Flipflop|-|&FB7E||FDC 765 Main Status Register (Port read only)|-|&FB7EFB7F||FDC 765 Data Register (read/write) |} The Main Status Register signalizes when the FDC is ready to send/receive the next byte through the Data Register. The Data Register is used to write Commands and Parameters, to read/write data bytes, and to receive result bytes. These 3 operations are: * Command Phase: A command consists of a command byte (eventually including the MT, MF, SK bits), and up to 8 parameter bytes.
The Data Register * Execution Phase: During this phase, the actual data is transferred (Port &FB7Fif any) is used to write Commands and Parameters, to read/write . Usually that are the data bytesfor the read/written sector(s), and to receive result bytes. These 3 operations are called except for the Format Track Command-, Execution-, in that case 4 bytes for each sector are transferred. During data transfers between the FDC and Result-Phasethe processor, the FDC must be serviced every 26µs (for MFM mode with CPC timings) or the FDC terminates the FDC command.
Command * Result Phase: A command consists of a command byte Returns up to 7 result bytes (eventually including depending on the MT, MF, SK bitscommand)that are containing status information. The Recalibrate and Seek Track commands do not return result bytes directly, instead the program must wait until the Main Status Register signalizes that the command has been completed, and up then it must (!) send a Sense Interrupt State command to 8 parameter 'terminate' the Seek/Recalibrate command. During the result phase, all the result bytes must be read. The FDC will not accept a new command until all the result bytesare read.
Execution PhaseNote: During this phase, Bit b10 of the actual data address port is transferred (if any). Usually that are reset as the data bytes for the read/written sector(s)FDC is seen as an expansion, except for the Format Track Command, in that case 4 bytes for each sector are transferredeven if it is an internal chip. During data transfers between Bit b7 is reset to select the FDC . Bits b8 and b0 are used to select the processor, the FDC must be serviced every 26µs (for MFM specific mode with CPC timings) or the FDC terminates the FDC commandof operation. All other bits should be set to 1 to avoid conflict. [https://www.cpc-power.com/cpcarchives/index.php?page=articles&num=48 Source]
Result PhaseNote2: Returns up to 7 result bytes (depending on the command) that are containing status information. The Recalibrate and Seek Track commands do not return result bytes directly, instead the program must wait until the Main Status Register signalizes that the command has been completed, and then it must (!) send a Sense Interrupt State command to 'terminate' the Seek/Recalibrate command[[Vortex Disc Drives|Vortex disc interface]] uses other ports. During the result phase, all the result bytes must be read. The FDC will not accept a new command until all the result bytes are readSee its dedicated wiki page.
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