The Z80/Z80A was a very popular microprocessor, used in a wide range of applications, from gaming consoles like the [[ColecoVision]], the [[Sega Master System]] and [[Sega GameGear]] to personal computers like the [[ZX81]], [[ZX Spectrum]] and [[MSX]].
It The Z80 was also used in the [[Commodore 64|Commodore C128]] as a secondary processor dual CPU in many computers in order to achieve have [[CP/M]] compatibility. Similarly, :* the [[Commodore 64|Commodore C128]] had one built-in* the Acorn Z80 Second Processor expansion for the [[BBC Micro]] enabled [[CP/M]] compatibility. And * the popular Z-80 SoftCard expansion did the same for the [[Apple II]].* the ATR8000 expansion for the [[Atari 8-bit]]* the Z80 CP/M expansion cartridge for the [[C64]]
The best-selling devices to feature a Zilog Z80 are the [[Sega MegaDrive]] with 40 million units sold [https://segaretro.org/Sega_Mega_Drive#:~:text=The%20Mega%20Drive%20is%20Sega%27s,and%203%20million%20in%20Brazil. Source], and the TI graphing calculators with 90 million units sold [https://drive.google.com/file/d/1PshC6_lvHiBqry2ASsZ5D0AonmW01nxQ/view Source].
The Z80 microprocessor is an 8-bit [[CPU]] with a 4-bit ALU and a 16-bit address bus capable of direct access to 64KB of memory space. The Z80 is a little-endian CPU, meaning it stores 16-bit values with the least significant byte first, followed by the most significant byte.
It has a language The Z80 instruction set is really 3 separate subsets each occupying 256 opcode ‘slots’. The main and CB subsets each occupy the full range of 252 root 256 instructions and with , while the reserved 4 bytes as ED subset is mostly empty and only implements 59 instructions. DD and FD instruction prefixes, access are not counted as they are just modifiers to an additional 308 use the index registers. This means there are 571 unique instructionsin the Z80 instruction set. Although it lacks the raw processing power of processors like the Intel 80x86 or the [[Motorola 68000]] series, the Z80 is extremely useful for low cost control applications.
The Z80 has about 8500 transistors. To put it into perspective, 64KB of DRAM contains 524288 transistors, as 1 bit of DRAM needs 1 transistor. Fun fact: an Amstrad CPC equipped with a 4MB RAM expansion has 32 million transistors dedicated to RAM while the Z80 CPU still has only 8500 transistors.
* P = parity (only for the parity flag)
* V = overflow (only for the parity flag)
* A = OR with the respective bit of the accumulator
* C = set if the counter (bc) is nonzero after decrementing
==== Registers ====
! Instruction !! Opcode !! Hexcode !! NOPs !! Cycles !! M-Cycle Sequence !! S !! Z !! 5 !! H !! 3 !! P !! N !! C !! Effect !! Description
|-
| ld r,r̃ || 01rrrr̃r̃r̃ || 40-6F/78-7F || 1 || 4 (4) || M1 || rowspan=15|- || rowspan=15|- || rowspan=15|- || rowspan=15|- || rowspan=15|- || rowspan=15|- || rowspan=15|- || rowspan=15|- || r := r̃ ||rowspan=15|8-bit Load
|-
| ld (hl),r || 01110rrr || 70/71/72/73/74/75/77 || 2 || 7 (4,3) || M1, MW || (hl) := r
| ld r,(hl) || 01rrr110 || 46/4E/56/5E/66/6E/7E || 2 || 7 (4,3) || M1, MR || r := (hl)
|-
| ld s,s̃ || 01ssss̃s̃s̃ || DD/FD 40-6F/78-7F || 2 || 8 (4,4) || M1, M1 || s := s̃
|-
| ld (ixy+d),r || 01110rrr || DD/FD 70/71/72/73/74/75/77 dd || 5 || 19 (4,4,3,5,3) || M1, M1, MRd, INT(5), MW || (ixy+d) := r
|| Decimal Adjust Accumulator
|-
| rrd || 01100111 || ED 67 || 5 || 18 (4,4,3,4,3) || M1, M1, MR, INT(4), MW || + || + || + || 0 || + || P || 0 || - || tmp := (hl), (hl) := [tmp >> 4] + [[a and 0x0f] << 4],<br> a := [a and 0xf0] + [tmp and 0x0f] => flags
|| Rotate Right Decimal
|-
| rld || 01101111 || ED 6F || 5 || 18 (4,4,3,4,3) || M1, M1, MR, INT(4), MW || + || + || + || 0 || + || P || 0 || - || tmp := [(hl) << 4] + [a and 0x0f], (hl) := tmp,<br> a := [a and 0xf0] + [tmp >> 8] => flags
|| Rotate Left Decimal
|}
| rra || 00011111 || 1F || 1 || 4 (4) || M1 || ocf := cf, cf := a.0, a := [a >> 1] + [ocf << 7]
|-
| rlc r || 00000rrr || CB 00-/01/02/03/04/05/07 || 2 || 8 (4,4) || M1, M1 || rowspan=4|+ || rowspan=4|+ || rowspan=4|+ || rowspan=4|0 || rowspan=4|+ || rowspan=4|P || rowspan=4|0 || rowspan=4|X || cf := r.7, r := [r << 1] + cf ||rowspan=4|Rotate Left Carry
|-
| rlc (ixy+d)->r || 00000rrr || DD/FD CB dd 00-/01/02/03/04/05/07 || 7 || 23 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || cf := (ixy+d).7, (ixy+d) := r := [(ixy+d) << 1] + cf
|-
| rlc (hl) || 00000110 || CB 06 || 4 || 15 (4,4,4,3) || M1, M1, MR, INT(1), MW || cf := (hl).7, (hl) := [(hl) << 1] + cf
| rlc (ixy+d) || 00000110 || DD/FD CB dd 06 || 7 || 23 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || cf := (ixy+d).7, (ixy+d) := [(ixy+d) << 1] + cf
|-
| rrc r || 00001rrr || CB 08-/09/0A/0B/0C/0D/0F || 2 || 8 (4,4) || M1, M1 || rowspan=4|+ || rowspan=4|+ || rowspan=4|+ || rowspan=4|0 || rowspan=4|+ || rowspan=4|P || rowspan=4|0 || rowspan=4|X || cf := r.0, r := [r >> 1] + [cf << 7] ||rowspan=4|Rotate Right Carry
|-
| rrc (ixy+d)->r || 00001rrr || DD/FD CB dd 08-/09/0A/0B/0C/0D/0F || 7 || 23 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || cf := (ixy+d).0, (ixy+d) := r := [(ixy+d) >> 1] + [cf << 7]
|-
| rrc (hl) || 00001110 || CB 0E || 4 || 15 (4,4,4,3) || M1, M1, MR, INT(1), MW || cf := (hl).0, (hl) := [(hl) >> 1] + [cf << 7]
| rrc (ixy+d) || 00001110 || DD/FD CB dd 0E || 7 || 23 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || cf := (ixy+d).0, (ixy+d) := [(ixy+d) >> 1] + [cf << 7]
|-
| rl r || 00010rrr || CB 10-/11/12/13/14/15/17 || 2 || 8 (4,4) || M1, M1 || rowspan=4|+ || rowspan=4|+ || rowspan=4|+ || rowspan=4|0 || rowspan=4|+ || rowspan=4|P || rowspan=4|0 || rowspan=4|X || ocf := cf, cf := r.7, r := [r << 1] + ocf ||rowspan=4|Rotate Left
|-
| rl (ixy+d)->r || 00010rrr || DD/FD CB dd 10-/11/12/13/14/15/17 || 7 || 23 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || ocf := cf, cf := (ixy+d).7, (ixy+d) := r := [(ixy+d) << 1] + ocf
|-
| rl (hl) || 00010110 || CB 16 || 4 || 15 (4,4,4,3) || M1, M1, MR, INT(1), MW || ocf := cf, cf := (hl).7, (hl) := [(hl) << 1] + ocf
| rl (ixy+d) || 00010110 || DD/FD CB dd 16 || 7 || 23 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || ocf := cf, cf := (ixy+d).7, (ixy+d) := [(ixy+d) << 1] + ocf
|-
| rr r || 00011rrr || CB 18-/19/1A/1B/1C/1D/1F || 2 || 8 (4,4) || M1, M1 || rowspan=4|+ || rowspan=4|+ || rowspan=4|+ || rowspan=4|0 || rowspan=4|+ || rowspan=4|P || rowspan=4|0 || rowspan=4|X || ocf := cf, cf := r.0, r := [r >> 1] + [ocf << 7] ||rowspan=4|Rotate Right
|-
| rr (ixy+d)->r || 00011rrr || DD/FD CB dd 18-/19/1A/1B/1C/1D/1F || 7 || 23 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || ocf := cf, cf := (ixy+d).0, (ixy+d) := r := [(ixy+d) >> 1] + [ocf << 7]
|-
| rr (hl) || 00011110 || CB 1E || 4 || 15 (4,4,4,3) || M1, M1, MR, INT(1), MW || ocf := cf, cf := (hl).0, (hl) := [(hl) >> 1] + [ocf << 7]
| rr (ixy+d) || 00011110 || DD/FD CB dd 1E || 7 || 23 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || ocf := cf, cf := (ixy+d).0, (ixy+d) := [(ixy+d) >> 1] + [ocf << 7]
|-
| sla r || 00100rrr || CB 20-/21/22/23/24/25/27 || 2 || 8 (4,4) || M1, M1 || rowspan=4|+ || rowspan=4|+ || rowspan=4|+ || rowspan=4|0 || rowspan=4|+ || rowspan=4|P || rowspan=4|0 || rowspan=4|X || cf := r.7, r := r << 1 ||rowspan=4|Shift Left Arithmetic
|-
| sla (ixy+d)->r || 00100rrr || DD/FD CB dd 20-/21/22/23/24/25/27 || 7 || 23 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || cf := (ixy+d).7, (ixy+d) := r := (ixy+d) << 1
|-
| sla (hl) || 00100110 || CB 26 || 4 || 15 (4,4,4,3) || M1, M1, MR, INT(1), MW || cf := (hl).7, (hl) := (hl) << 1
| sla (ixy+d) || 00100110 || DD/FD CB dd 26 || 7 || 23 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || cf := (ixy+d).7, (ixy+d) := (ixy+d) << 1
|-
| sra r || 00101rrr || CB 28-/29/2A/2B/2C/2D/2F || 2 || 8 (4,4) || M1, M1 || rowspan=4|+ || rowspan=4|+ || rowspan=4|+ || rowspan=4|0 || rowspan=4|+ || rowspan=4|P || rowspan=4|0 || rowspan=4|X || cf := r.0, r := r >> 1, r.7 := r.6 ||rowspan=4|Shift Right Arithmetic
|-
| sra (ixy+d)->r || 00101rrr || DD/FD CB dd 28-/29/2A/2B/2C/2D/2F || 7 || 23 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || cf := (ixy+d).0, tmp := (ixy+d) >> 1, tmp.7 := tmp.6, (ixy+d) := r := tmp
|-
| sra (hl) || 00101110 || CB 2E || 4 || 15 (4,4,4,3) || M1, M1, MR, INT(1), MW || cf := (hl).0, (hl) := (hl) >> 1, (hl).7 := (hl).6
| sra (ixy+d) || 00101110 || DD/FD CB dd 2E || 7 || 23 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || cf := (ixy+d).0, (ixy+d) := (ixy+d) >> 1, (ixy+d).7 := (ixy+d).6
|-
| sll r || 00110rrr || CB 30-/31/32/33/34/35/37 || 2 || 8 (4,4) || M1, M1 || rowspan=4|+ || rowspan=4|+ || rowspan=4|+ || rowspan=4|0 || rowspan=4|+ || rowspan=4|P || rowspan=4|0 || rowspan=4|X || cf := r.7, r := [r << 1] + 1 ||rowspan=4|Shift Left Logical
|-
| sll (ixy+d)->r || 00110rrr || DD/FD CB dd 30-/31/32/33/34/35/37 || 7 || 23 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || cf := (ixy+d).7, (ixy+d) := r := [(ixy+d) << 1] + 1
|-
| sll (hl) || 00110110 || CB 36 || 4 || 15 (4,4,4,3) || M1, M1, MR, INT(1), MW || cf := (hl).7, (hl) := [(hl) << 1] + 1
| sll (ixy+d) || 00110110 || DD/FD CB dd 36 || 7 || 23 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || cf := (ixy+d).7, (ixy+d) := [(ixy+d) << 1] + 1
|-
| srl r || 00111rrr || CB 38-/39/3A/3B/3C/3D/3F || 2 || 8 (4,4) || M1, M1 || rowspan=4|0 || rowspan=4|+ || rowspan=4|+ || rowspan=4|0 || rowspan=4|+ || rowspan=4|P || rowspan=4|0 || rowspan=4|X || cf := r.0, r := r >> 1 ||rowspan=4|Shift Right Logical
|-
| srl (ixy+d)->r || 00111rrr || DD/FD CB dd 38-/39/3A/3B/3C/3D/3F || 7 || 23 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || cf := (ixy+d).0, (ixy+d) := r := (ixy+d) >> 1
|-
| srl (hl) || 00111110 || CB 3E || 4 || 15 (4,4,4,3) || M1, M1, MR, INT(1), MW || cf := (hl).0, (hl) := (hl) >> 1
{| class="wikitable" style="white-space: nowrap;"
|-
! Instruction !! Opcode !! Hexcode !! NOPs !! Cycles !! M-Cycle Sequence !! S !! Z !! 5 !! H !! 3 !! P !! N !! C !! Effect !! Description
|-
| bit b,r || CB 01bbbrrr || CB 40-7F || 2 || 8 (4,4) || M1, M1 || + || + || + || 1 || + || P || 0 || - || tmp := r and [1 << b] ||rowspan=3|Test Bit
|-
| bit b,(hl) || CB 01bbb110 || CB 46/4E/56/5E/66/6E/76/7E || 3 || 12 (4,4,4) || M1, M1, MR, INT(1) || + || + || X || 1 || X || P || 0 || - || tmp := (hl) and [1 << b],<br> f5 := wz.13, f3 := wz.11
|-
| bit b,(ixy+d) || 01bbb110 || DD/FD CB dddddddd 01bbb*** dd 46/4E/56/5E/66/6E/76/7E || 6 || 20 (4,4,3,5,4) || M1, M1, MRd, MRo, INT(2), MR, INT(1) || + || + || X || 1 || X || P || 0 || - || tmp := (ixy+d) and [1 << b],<br> f5 := [ixy+d].13, f3 := [ixy+d].11
|-
| res b,r || CB 10bbbrrr || CB 80-BF || 2 || 8 (4,4) || M1, M1 || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || r := r and ~[1 << b] ||rowspan=4|Reset Bit
|-
| res b,(hlixy+d) ->r || 10bbbrrr || DD/FD CB 10bbb110 dd 80-BF || 4 7 || 15 23 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || (hlixy+d) := r := (hlixy+d) and ~[1 << b]
|-
| res b,(ixy+dhl) || DD/FD CB dddddddd 10bbb110 || 7 CB 86/8E/96/9E/A6/AE/B6/BE || 4 || 23 15 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || (ixy+dhl) := (ixy+dhl) and ~[1 << b]
|-
| res b,(ixy+d)->r || 10bbb110 || DD/FD CB dddddddd 10bbbrrr dd 86/8E/96/9E/A6/AE/B6/BE || 7 || 23 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || (ixy+d) := r := (ixy+d) and ~[1 << b]
|-
| set b,r || CB 11bbbrrr || CB C0-FF || 2 || 8 (4,4) || M1, M1 || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || r := r or [1 << b] ||rowspan=4|Set Bit
|-
| set b,(hlixy+d) ->r || 11bbbrrr || DD/FD CB 11bbb110 dd C0-FF || 4 7 || 15 23 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || (hlixy+d) := r := (hlixy+d) or [1 << b]
|-
| set b,(ixy+dhl) || DD/FD CB dddddddd 11bbb110 || 7 CB C6/CE/D6/DE/E6/EE/F6/FE || 4 || 23 15 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || (ixy+dhl) := (ixy+dhl) or [1 << b]
|-
| set b,(ixy+d)->r || 11bbb110 || DD/FD CB dddddddd 11bbbrrr dd C6/CE/D6/DE/E6/EE/F6/FE || 7 || 23 (4,4,3,5,4,3) || M1, M1, MRd, MRo, INT(2), MR, INT(1), MW || (ixy+d) := r := (ixy+d) or [1 << b]
|-
| cpl || 00101111 || 2F || 1 || 4 (4) || M1 || - || - || + || 1 || + || - || 1 || - || a := ~a || Complement
|-
| neg || ED 01***100 || ED 44/4C/54/5C/64/6C/74/7C || 2 || 8 (4,4) || M1, M1 || + || + || + || + || + || V || 1 || + || a := - a || Negate
|}
{| class="wikitable" style="white-space: nowrap;"
|-
! Instruction !! Opcode !! Hexcode !! NOPs !! Cycles !! M-Cycle Sequence !! S !! Z !! 5 !! H !! 3 !! P !! N !! C !! Effect !! Description
|-
| ldir ldi || 10100000 || ED 10110000 A0 || 6/5 || 21/16 (4,4,3,5,5)/(4,4,3,5) || M1, M1, MR, MW, INT(2)(, INT(5)) || rowspan=4|- || rowspan=4|- || rowspan=4|X || rowspan=4|0 || rowspan=4|X || rowspan=4|C X || rowspan=4|0 || rowspan=4|- || lditmp := (hl), (de) := tmp, de += 1, hl += 1, if bc <br> 0 then pc bc -= 2 1, pf := bc!=0, f5 := [tmp + a].1, f3 := [tmp + a].3 || rowspan=4|Block Load
|-
| lddr ldd || 10101000 || ED 10111000 A8 || 6/5 || 21/16 (4,4,3,5,5)/(4,4,3,5) || M1, M1, MR, MW, INT(2)|| tmp := (hl), INT(5de)) || ldd:= tmp, de -= 1, hl -= 1, if bc <br> 0 then pc bc -= 21, pf := bc!=0, f5 := [tmp + a].1, f3 := [tmp + a].3
|-
| ldi ldir || 10110000 || ED 10100000 B0 || 6/5 || 21/16 (4,4,3,5,5)/(4,4,3,5) || M1, M1, MR, MW, INT(2) || tmp := (hl), INT(de5) := tmp) || ldi, de += 1, hl += 1,if bc != 0 then pc -= 1, f5 := [tmp + a].1, f3 := [tmp + a].32
|-
| ldd lddr || 10111000 || ED 10101000 B8 || 6/5 || 21/16 (4,4,3,5,5)/(4,4,3,5) || M1, M1, MR, MW, INT(2) || tmp := (hl), INT(de5) := tmp) || ldd, de -if bc != 1, hl 0 then pc -= 1,bc -= 1, f5 := [tmp + a].1, f3 := [tmp + a].32
|-
| cpir cpi || 10100001 || ED 10110001 A1 || 6/4 || 21/16 (4,4,3,5,5)/(4,4,3,5) || M1, M1, MR, INT(5)(, INT(5)) || rowspan=4|+ || rowspan=4|+ || rowspan=4|X || rowspan=4|+ || rowspan=4|X || rowspan=4|C X || rowspan=4|1 || rowspan=4|- || cpitmp := a - (hl) => flags, hl += 1, if bc <br> bc -= 1, pf := bc!=0 and nz then pc , f5 := [tmp -hf].1, f3 = 2 [tmp - hf].3 || rowspan=4| Block Compare
|-
| cpdr cpd || 10101001 || ED 10111001 A9 || 6/4 || 21/16 (4,4,3,5,5)/(4,4,3,5) || M1, M1, MR, INT(5)(, INT(5)) || cpdtmp := a - (hl) => flags, hl -= 1, if bc <br> bc -= 1, pf := bc!=0 and nz then pc , f5 := [tmp -hf].1, f3 = 2[tmp - hf].3
|-
| cpi cpir || 10110001 || ED 10100001 B1 || 6/4 || 21/16 (4,4,3,5,5)/(4,4,3,5) || M1, M1, MR, INT(5) || tmp := a - (hl, INT(5) => flags) || cpi, if bc -!= 1, hl += 1,f5 := [tmp 0 and nz then pc - hf].1, f3 = [tmp - hf].32
|-
| cpd cpdr || 10111001 || ED 10101001 B9 || 6/4 || 21/16 (4,4,3,5,5)/(4,4,3,5) || M1, M1, MR, INT(5) || tmp := a - (hl, INT(5) => flags) || cpd, if bc -!= 1, hl 0 and nz then pc -= 1,f5 := [tmp - hf].1, f3 = [tmp - hf].32
|-
| inir ini || 10100010 || ED 10110010 A2 || 6/5 || 21/16 (4,5,4,3,5)/(4,5,4,3) || M1, M1, INT(1), IOR, MW(, INT(5)) || rowspan=4|+ || rowspan=4|+ || rowspan=4|+ || rowspan=4|X || rowspan=4|+ || rowspan=4|X || rowspan=4|X 1 || rowspan=4|X || initmp := ((c)), (hl) := tmp, hl += 1, if b <br> 0 then pc b -= 2 1 => flags, <br> tmp2 := tmp + [[c + 1] and 0xff], <br> pf := parity of [[tmp2 and 0x07] xor b], <br> hf := cf := tmp2 > 255 || rowspan=4|Block I/O Input
|-
| indr ind || 10101010 || ED 10111010 AA || 6/5 || 21/16 (4,5,4,3,5)/(4,5,4,3) || M1, M1, INT(1), IOR, MW|| tmp := (, INT(5c)) || ind, if (hl) := tmp, hl -= 1, <br> b -= 1 => flags, <br> 0 then pc tmp2 = tmp + [[c -1] and 0xff], <br> pf := 2parity of [[tmp2 and 0x07] xor b], <br> hf := cf := tmp2 > 255
|-
| ini inir || 10110010 || ED 10100010 B2 || 6/5 || 21/16 (4,5,4,3,5)/(4,5,4,3) || M1, M1, INT(1), IOR, MW || tmp := (, INT(c5))|| ini, (hl) :if b != tmp, hl += 1,b 0 then pc -= 1 => flags, nf := tmp.7, tmp2 := tmp + [[c + 1] and 0xff], pf := parity of [[tmp2 and 0x07] xor b], hf := cf := tmp2 > 2552
|-
| ind indr || 10111010 || ED 10101010 BA || 6/5 || 21/16 (4,5,4,3,5)/(4,5,4,3) || M1, M1, INT(1), IOR, MW || tmp := (, INT(c5))|| ind, (hl) := tmp, hl -= 1,if b -!= 1 => flags, nf := tmp.7, tmp2 = tmp + [[c 0 then pc - 1] and 0xff], pf := parity of [[tmp2 and 0x07] xor b], hf := cf := tmp2 > 2552
|-
| otir outi || 10100011 || ED 10110011 A3 || 6/5 || 21/16 (4,5,3,4,5)/(4,5,3,4) || M1, M1, INT(1), MR, IOW(, INT(5)) || rowspan=4|+ || rowspan=4|+ || rowspan=4|+ || rowspan=4|X || rowspan=4|+ || rowspan=4|X || rowspan=4|X 1 || rowspan=4|X || outitmp := (hl), ((c)) := tmp, hl += 1, if b <br> 0 then pc b -= 2 1 => flags, tmp2 = tmp + l, <br> pf := parity of [[tmp2 and 0x07] xor b], <br> hf := cf := tmp2 > 255 || rowspan=4|Block I/O Output
|-
| otdr outd || 10101011 || ED 10111011 AB || 6/5 || 21/16 (4,5,3,4,5)/(4,5,3,4) || M1, M1, INT(1), MR, IOW|| tmp := (hl), INT(5(c)) || outd:= tmp, hl -= 1, if b <br> 0 then pc b -= 21 => flags, tmp2 = tmp + l, <br> pf := parity of [[tmp2 and 0x07] xor b], <br> hf := cf := tmp2 > 255
|-
| outi otir || 10110011 || ED 10100011 B3 || 6/5 || 21/16 (4,5,3,4,5)/(4,5,3,4) || M1, M1, INT(1), MR, IOW || tmp := (hl), INT((c5)) := tmp|| outi, hl +if b != 1,b 0 then pc -= 1 => flags, nf := tmp.7, tmp2 = tmp + l, pf := parity of [[tmp2 and 0x07] xor b], hf := cf := tmp2 > 2552
|-
| outd otdr || 10111011 || ED 10101011 BB || 6/5 || 21/16 (4,5,3,4,5)/(4,5,3,4) || M1, M1, INT(1), MR, IOW || tmp := (hl), INT((c5)) := tmp|| outd, hl -if b != 1,b 0 then pc -= 1 => flags, nf := tmp.7, tmp2 = tmp + l, pf := parity of [[tmp2 and 0x07] xor b], hf := cf := tmp2 > 2552
|}
{| class="wikitable" style="white-space: nowrap;"
|-
! Instruction !! Opcode !! Hexcode !! NOPs !! Cycles !! M-Cycle Sequence !! S !! Z !! 5 !! H !! 3 !! P !! N !! C !! Effect !! Description
|-
| in a,(n) || 11011011 nnnnnnnn || DB nn || 3 || 11 (4,3,4) || M1, MRn, IOR || - || - || - || - || - || - || - || - || a := ((n)) ||rowspan=3|I/O Input
|-
| in r,(c) || ED 01rrr000 || ED 40/48/50/58/60/68/78 || 4 || 12 (4,4,4) || M1, M1, IOR || + || + || + || 0 || + || P || 0 || - || r := ((c))
|-
| in f,(c) || ED 01110000 || ED 70 || 4 || 12 (4,4,4) || M1, M1, IOR || + || + || + || 0 || + || P || 0 || - || tmp := ((c))
|-
| out (n),a || 11010011 nnnnnnnn || D3 nn || 3 || 11 (4,3,4) || M1, MRn, IOW || - || - || - || - || - || - || - || - || ((n)) := a ||rowspan=3| I/O Output
|-
| out (c),r || ED 01rrr001 || ED 41/49/51/59/61/69/79 || 4 || 12 (4,4,4) || M1, M1, IOW || - || - || - || - || - || - || - || - || ((c)) := r
|-
| out (c),0 || ED 01110001 || ED 71 || 4 || 12 (4,4,4) || M1, M1, IOW || - || - || - || - || - || - || - || - || ((c)) := 0 (or 255 on CMOS CPU)
|}
{| class="wikitable" style="white-space: nowrap;"
|-
! Instruction !! Opcode !! Hexcode !! NOPs !! Cycles !! M-Cycle Sequence !! S !! Z !! 5 !! H !! 3 !! P !! N !! C !! Effect !! Description
|-
| rst t || 11ttt111 || C7/CF/D7/DF/E7/EF/F7/FF || 4 || 11 (5,3,3) || M1, MW, MW || rowspan=3|- || rowspan=3|- || rowspan=3|- || rowspan=3|- || rowspan=3|- || rowspan=3|- || rowspan=3|- || rowspan=3|- || sp -= 2, (sp) := pc, pc := t || Restart<br> ttt: 000=#0, 001=#8, 010=#10, 011=#18, 100=#20, 101=#28, 110=#30, 111=#38
|-
| call nn || 11001101 lolololo hihihihi || CD lo hi || 5 || 17 (4,3,4,3,3) || M1, MRl, MRh, INT(1), MW, MW || sp -= 2, (sp) := pc, pc := nn || Call
|-
| call cc,nn || 11ccc100 lolololo hihihihi || C4/CC/D4/DC/E4/EC/F4/FC lo hi || 5/3 || 17/10 (4,3,4,3,3)/(4,3,3) || M1, MRl, MRh(, INT(1), MW, MW) || if cc then sp -= 2, (sp) := pc, pc := nn || Conditional call<br> ccc: 000=NZ, 001=Z, 010=NC, 011=C, 100=PO, 101=PE, 110=P, 111=M
|-
| jp nn (hl) || 11000011 lolololo hihihihi 11101001 || 3 E9 || 10 1 || 4 (4,3,3) || M1, MRl, MRh || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || pc := nn hl ||rowspan=3|Jump
|-
| jp (hlixy) || 11101001 || 1 DD/FD E9 || 4 2 || 8 (4,4) || M1, M1 || pc := hlixy
|-
| jp (ixy) nn || DD/FD 11101001 11000011 || 2 C3 lo hi || 8 3 || 10 (4,43,3) || M1, M1 MRl, MRh || pc := ixynn
|-
| jp cc,nn || 11ccc010 lolololo hihihihi || C2/CA/D2/DA/E2/EA/F2/FA lo hi || 3 || 10 (4,3,3) || M1, MRl, MRh || if cc then pc := nn || Conditional jump<br> ccc: 000=NZ, 001=Z, 010=NC, 011=C, 100=PO, 101=PE, 110=P, 111=M
|-
| jr e || 00011000 eeeeeeee || 18 ee || 3 || 12 (4,3,5) || M1, MRe, INT(5) || rowspan=3|- || rowspan=3|- || rowspan=3|- || rowspan=3|- || rowspan=3|- || rowspan=3|- || rowspan=3|- || rowspan=3|- || pc += e || Relative jump
|-
| jr cc,e || 001cc000 eeeeeeee || 20/28/30/38 ee || 3/2 || 12/7 (4,3,5)/(4,3) || M1, MRe(, INT(5)) || if cc then pc += e || Conditional relative jump<br> cc: 00=NZ, 01=Z, 10=NC, 11=C
|-
| djnz e || 00010000 eeeeeeee || 10 ee || 4/3 || 13/8 (5,3,5)/(5,3) || M1, INT(1), MRe(, INT(5)) || b -= 1, if b <> != 0 then pc += e || Decrement, Jump Non-Zero
|-
| ret || 11001001 || C9 || 3 || 10 (4,3,3) || M1, MR, MR || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || rowspan=4|- || pc := (sp), sp += 2 || Return
|-
| ret cc || 11ccc000 || C0/C8/D0/D8/E0/E8/F0/F8 || 4/2 || 11/5 (5,3,3)/(5) || M1, INT(1)(, MR, MR) || if cc then pc := (sp), sp += 2 || Conditional return<br> ccc: 000=NZ, 001=Z, 010=NC, 011=C, 100=PO, 101=PE, 110=P, 111=M
|-
| reti || ED 01001101 || ED 4D || 4 || 14 (4,4,3,3) || M1, M1, MR, MR || pc := (sp), sp += 2, iff1 := iff2 || Return from Interrupt
|-
| retn || ED 01***101 || ED 45/55/5D/65/6D/75/7D || 4 || 14 (4,4,3,3) || M1, M1, MR, MR || pc := (sp), sp += 2, iff1 := iff2 || Return from NMI
|}
{| class="wikitable" style="white-space: nowrap;"
|-
! Instruction !! Opcode !! Hexcode !! NOPs !! Cycles !! M-Cycle Sequence !! S !! Z !! 5 !! H !! 3 !! P !! N !! C !! Effect !! Description
|-
| ld i,a || ED 01000111 || ED 47 || 3 || 9 (4,5) || M1, M1, INT(1) || - || - || - || - || - || - || - || - || i := a || rowspan=4|CPU State Load
|-
| ld r,a || ED 01001111 || ED 4F || 3 || 9 (4,5) || M1, M1, INT(1) || - || - || - || - || - || - || - || - || r := a
|-
| ld a,i || ED 01010111 || ED 57 || 3 || 9 (4,5) || M1, M1, INT(1) || + || + || + || 0 || + || X || 0 || - || a := i, pf := iff2
|-
| ld a,r || ED 01011111 || ED 5F || 3 || 9 (4,5) || M1, M1, INT(1) || + || + || + || 0 || + || X || 0 || - || a := r, pf := iff2
|-
| di || 11110011 || F3 || 1 || 4 (4) || M1 || - || - || - || - || - || - || - || - || iff1 := 0, iff2 := 0 || Disable Interrupts
|-
| ei || 11111011 || FB || 1 || 4 (4) || M1 || - || - || - || - || - || - || - || - || iff1 := 1, iff2 := 1 after the next instruction || Enable Interrupts
|-
| im m || ED 01mmm110 || ED 46/4E/56/5E/66/6E/76/7E || 2 || 8 (4,4) || M1, M1 || - || - || - || - || - || - || - || - || im := m ||Set Interrupt Mode<br> mmm: 000=0, 001=0, 010=1, 011=2, 100=0, 101=0, 110=1, 111=2
|-
| halt || 01110110 || 76 || 1 || 4 (4) || M1 || - || - || - || - || - || - || - || - || wait for interrupt || Suspends CPU operation
|-
| nop || 00000000 || 00000000 || 1 || 4 (4) || M1 || - || - || - || - || - || - || - || - || nothing ||No Operation
|-
| scf || 00110111 || 37 || 1 || 4 (4) || M1 || - || - || A X || 0 || A X || - || 0 || 1 || nothing else f5 := f5 or a.5, f3 := f3 or a.3 || Set Carry Flag
|-
| ccf || 00111111 || 3F || 1 || 4 (4) || M1 || - || - || A X || X || A X || - || 0 || X || hf := cf, cf := ~cf , f5 := f5 or a.5, f3 := f3 or a.3 || Complement Carry Flag|-| exx || 11011001 || D9 || 1 || 4 (4) || M1 || - || - || - || - || - || - || - || - || bc, de, hl <=> bc', de', hl' ||rowspan=5|Exchange|-| ex de,hl || 11101011 || EB || 1 || 4 (4) || M1 || - || - || - || - || - || - || - || - || de <=> hl|-| ex (sp),hl || 11100011 || E3 || 6 || 19 (4,3,4,3,5) || M1, MR, MR, INT(1), MW, MW, INT(2) || - || - || - || - || - || - || - || - || (sp) <=> hl|-| ex (sp),ixy || 11100011 || DD/FD E3 || 7 || 23 (4,4,3,4,3,5) || M1, M1, MR, MR, INT(1), MW, MW, INT(2) || - || - || - || - || - || - || - || - || (sp) <=> ixy|-| ex af,af' || 00001000 || 08 || 1 || 4 (4) || M1 || X || X || X || X || X || X || X || X || af <=> af'|} <br> === Interrupt Acknowledge === {| class="wikitable" style="white-space: nowrap;"
|-
| exx || 11011001 || 1 || 4 (4) || M1 || ! Type !! Cycles !! M- || - || - || - || - || - || - || - || bc, de, hl <=> bc', de', hl' ||rowspan=5|ExchangeCycle Sequence !! Effect !! Description
|-
| ex de,hl Non-Maskable Interrupt || 11101011 11 (5, 3, 3) || M1, Int(1 || 4 ), MW (4Push PCH), MW (Push PCL) || M1 || iff2 := iff1, iff1 := 0, sp - = 2, (sp) := pc, pc := 0066h || - || - || - || - || - || - || - || de <=> hlHighest priority interrupt. Cannot be disabled by `DI`. Fixed vector address. Saves previous IFF1 state.
|-
| ex (sp),hl Interrupt in Mode 0 || 11100011 || 6 || 19 13+ (4,3,4,3,5Typically 13 for RST) || M1(IntAck + 2wait), MR, MR, INTInt(1), plus cycles for fetched instruction (e.g., MW, MW, INT(2for RST) || - Fetches instruction from Data Bus during acknowledge cycle; Executes fetched instruction (usually `RST nn`) || 8080 compatible mode. Relies on interrupting peripheral to supply an instruction byte (typically `RST`). Cycle count depends on the instruction supplied (13T is for a 1- || - || - || - || - || - || - || (spbyte `RST`) <=> hl.
|-
| ex (sp),ixy || DD/FD 11100011 Interrupt in Mode 1 || 13 (7 || 23 (4,4,3,4,3,5) || M1(IntAck + 2wait), M1, MR, MR, INTInt(1), MW(Push PCH), MW, INT(2Push PCL) || iff1 := 0, sp - || - || - || - || - || - || - || - || = 2, (sp) <:=> ixypc, pc := 0038h || Simple mode, always jumps to fixed address `0038h`. No data needed from peripheral during acknowledge.
|-
| ex af,af' Interrupt in Mode 2 || 00001000 19 (7, 3, 3, 3, 3) || M1 (IntAck + 2wait), Int(1 || 4 ), MW (4Push PCH), MW (Push PCL), MR (Read Vector Low), MR (Read Vector High) || M1 || X || X || X || X || X || X || X || X || af <iff1 := 0, sp -= 2, (sp) := pc, pc :=> af'''('''(I << 8) + V''')''' || Most flexible mode. Forms pointer `(I * 256) + V` where `V` is vector byte from peripheral (LSB ignored). Reads 16-bit target address from pointer address. `I` register must be set up beforehand.
|}
* At the end of an NMI service routine, the earliest moment a maskable interrupt will be triggered is at the end of the instruction following RETN. [https://spectrumcomputing.co.uk/forums/viewtopic.php?t=7086 Source]
* RST instructions are just a CALL instruction to a fixed address baked in the instruction itself.
* JP cc,nn instruction consistently takes 10 T-states, no matter if the jump is taken or not.
* Unlike the conditional JP, CALL, RET instructions which have access to all conditions, JR is limited to NZ, Z, NC, C conditions.
* Despite what the syntax of the instructions JP (HL/IX/IY) suggests, PC will be loaded with the contents of the register itself, not the indexed value. Those instructions should be understood as JP HL/IX/IY.