On MSX, bus arbitration only applies to M1 machine cycles but access to VRAM has other limitations. On ZX Spectrum, bus arbitration is done not by using the /WAIT pin but by disabling the CPU clock when needed.
On CPC, bus arbitration occurs on every CPU bus access. The [[Gate Array]] asserts the /WAIT pin on the Z80 for 3 out of every 4 cycles, effectively aligning all bus operations to a 4-tick cycle. The Z80 extends T2 indefinitely by adding wait states until /WAIT is released.
The NOPs column corresponds to CPC timings, which account for the bus arbitration. The NOP instruction takes 4 cycles. This is the minimum amount of cycles an instruction can take.