It's important to note that the CRTC chip is primarily designed for character-based displays. It explains why, on the Amstrad CPC, the video memory is organized into a grid of characters rather than a purely linear bitmap.
NOTESNOTE: * This document describes the functionality in terms of the CPC with its separate CRTC and Gate-Array. The Plus has both integrated into the same IC, but could be considered to have two functional blocks, one for CRTC and one for Gate-Array. In this document the term 'Gate-Array' is used, but this also applies to the ASIC.* '''This article relies largely on a single source and is suspected of infringing copyright protected under the [https://creativecommons.org/licenses/by-nc-nd/4.0/legalcode CC BY-NC-ND 4.0 license].''' Readers are encouraged to refer directly to the original source material for accurate information. ** ''Original source material under copyright: [https://shaker.logonsystem.eu/ACCC1.8-EN.pdf The Amstrad CPC CRTC Compendium]''** ''Author: Serge Querné ([[Longshot]])'' <br>
== Overview ==
The 6845 Cathode Ray Tube Controller (CRTC) is a programmable IC used to generate video displays. This IC is used in a variety of computers including the Amstrad CPC, Amstrad Plus CPC+ and KC Compact. The CRTC is a simple chip. It is made up of counters and equality operators, tied by simple logic. All the complexity stems from its multiple independent implementations with their subtle differences.
The CRTC was a common part available from many different manufacturers. During the life of the CPC, Amstrad sourced the CRTC from various manufacturers.
This table lists the known ICs used, with their part number, manufacturer and type number.
{| class="wikitable"{{Prettytable|width: 700px; font-size: 2em;}}!|''Part number!''||''Manufacturer!''||''Type number (note 3)''
|-
|HD6845S||Hitachi||0
|AMS40489||Amstrad||3 (note 1)
|-
|AMS4022640226||Amstrad||4 (note 2)
|}
'''NOTES'''
1. The CRTC functionality is integrated into the CPC+ ASIC. This type exists only in the 464 PlusCPC464+, 6128 Plus CPC6128+ and GX4000.
2. This type exists in "cost-down" CPC464 and CPC6128 systems. In the "cost-down" the CRTC functionality is integrated into a single ASIC IC. This ASIC is often refered to as the "Pre-ASIC" because it preceeded the CPC+ ASIC. The CRTC functionality of the Pre-ASIC is almost identical to the CRTC within the ASIC.
3. In the Amstrad community each 6845 implementation has been assigned a type number. This type identifies a group of implementations which operate in exactly the same way. The type number system was originally used by demo programmers.
<br>As far as I know, the type number system was originally used by demo programmers.
==Programming==It is possible to detect the 6845 present using software methods, and this is done to:
The * warn that the software was not designed for the detected 6845 is selected when bit 14 of the I/O port address is set to "0". Bit 9 and 8 of the I/O port address define the may function incorrectly, * to access. The remaining bits can be any value, but adapt the software so that it is adviseable to set these to "1" to avoid conflict will run with other devices in the systemdetected 6845 * In most cases, the type of the detected 6845 is reported.
The recommended 4. As far as I/O port addresses are:know, the KC compact used HD6845R only.
{| class="wikitable"|-!I/O port address!/CS (A14)!R/W (A9)!RS (A8)!Function!Read/Write|-|&BCxx||0||0||0||Select 6845 register||Write only|-|&BDxx||0||0||1||Write to selected internal 6845 register||Write only|-|&BExx||0||1||0||* CRTCs 0/2: —* CRTC 1: Read Status Register* CRTCs 3/4: Read from selected internal 6845 register||Read only|-|&BFxx||0||1||1||Read from selected internal 6845 register||Read only|-|}= Timings and relating with Z80 instructions count ==
The CRTC is not connected to the CPU's RD and WR pins, so it cannot detect the bus's Some informations like : how many Z80 instructions can Ifit within a scan line ? Within a screen ? Etc... See http:/O direction/www. Therefore, executing an IN instruction to the select or write functions causes the CRTC to write the unpredictable data provided by the highcpcwiki.eu/forum/programming/frame-impedance bus flyback-and-interrupts/msg25106/#msg25106(To be extracted/edited to conform to its registerswiki good practices).
<br>==Programming==
=== Z80 The 6845 is selected when bit 14 of the I/O port address is set to "0". Bit 9 and 8 of the I/O port address define the function to access timings ===. The remaining bits can be any value, but it is adviseable to set these to "1" to avoid conflict with other devices in the system.
The clock provided to the CRTC by the ASICrecommended I/Pre-ASIC is phase-shifted compared to the one provided by the Gate Array.O port addresses are
{| class="wikitable"{{Prettytable|width: 700px; font-size: 2em;}}|+! Instructions !! Duration !! ''I/O CRTCs 0/1/2 !! I/O CRTCs 3port address''||''Function''||''Read/4Write''
|-
| OUT (C),r8 &BCxx|| 4 µsec Select 6845 register|| '''3rd µsec''' || 4th µsecWrite only
|-
| OUT (C),0 &BDxx|| 4 µsec Write 6845 register data|| '''3rd µsec''' || 4th µsecWrite only
|-
| OUT &BExx||(nnote 1),A || 3 µsec || 3rd µsec || 3rd µsecRead only
|-
| OUTI &BFxx|| 5 µsec (note 1)|| 5th µsec || 5th µsecRead only
|-
| OUTD || 5 µsec || 5th µsec || 5th µsec
|-
| IN r8,(C) || 4 µsec || 4th µsec || 4th µsec
|-
| INI || 5 µsec || '''4th µsec''' || '''4th µsec'''
|-
| IND || 5 µsec || '''4th µsec''' || '''4th µsec'''
|-
| IN A,(n) || 3 µsec || 3rd µsec || 3rd µsec
|}
<br>'''NOTE'''
==Video Memory Address (VMA)==1. The function of these I/O ports is dependant on the CRTC type 2. If you perform an IN instruction to the select or write functions it will write data to the CRTC from the current data on the bus.
The VMA of the [[Gate Array]] is constructed from the CRTC MA and RA signals:==Addressing==
The following table defines the generated memory address from the CRTC and Gate-Array signals. {| class="wikitable"{{Prettytable|width: 700px; font-size: 2em;}}!Video |''Memory Address!Signal''||''Signal source!''||''Signal name''
|-
|A15||6845||MA13
|A14||6845||MA12
|-
|A13||6845||'''RA2'''
|-
|A12||6845||'''RA1'''
|-
|A11||6845||'''RA0'''
|-
|A10||6845||MA9
|}
CRTC generates the address, Gate -Array reads the data and converts it to pixels based on its the current graphics mode and palette.
CRTC pins RA3, RA4, MA10, MA11 are not connected on CPC.== DISPTMG ==
<br> === Overscan bits === It is possible to use 32KB screen size (used for [[Programming:Overscan|overscan]]) by setting bits 11 and 10 of Register 12 both to 1DISPTMG signal defines the border. Bits MA11 and MA10 of the address generated by the CRTC are not written on the address bus to access video memory; settings both bits to 1 When DISPTMG is the only way to cause a carry to bit MA12 when address pass over the end of current video page to change the memory address to the next video page. {| class="wikitable"|+ CRTC Display Start Address|-! colspan="8" | Register 12! colspan="8" | Register 13|-! 15 !! 14 !! 13 !! 12 !! 11 !! 10 !! 9 !! 8! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0|-| colspan="2" | Unused| colspan="2" | Video Page| colspan="2" | Page Size| colspan="10" | Start Address (1024 positions)|} {| style="white-space: nowrap;"|-|{| class="wikitable" style="margin-right: 32px"|-! Bit 13 !! Bit 12 !! Video Page|-| 0 || 0 || 0000 - 3FFF|-| 0 || 1 || 4000 - 7FFF|-| 1 || 0 || 8000 - BFFF|-| 1 || 1 || C000 - FFFF|}|{| class="wikitable"|-! Bit 11 !! Bit 10 !! Page Size|-| 0 || 0 || 16KB|-| 0 || 1 || 16KB|-| 1 || 0 || 16KB|-| 1 || 1 || '''32KB'''|}|} <br> === Coarse hardware scrolling === The start address can be manipulated to achieve horizontal and/or vertical hardware scrolling: *To move right: <code>start_address := start_address + 1</code>*To move left: <code>start_address := start_address - 1</code>*To move down: <code>start_address := start_address + R1</code>*To move up: <code>start_address := start_address - R1</code> However, it is a position in word (16 bits), not in byte. So, the screen will move two bytes at a time horizontally. Also, the precision will be one CRTC character vertically. The first game that used R12/R13 for both horizontal and vertical hardware scrolling border colour is [https://www.cpc-power.com/index.php?page=detail&num=1839 Roland on the Ropes], released in 1984. The following BASIC program demonstrates the coarse scrolling output by setting the R12 and R13 registers based on keyboard input: <pre>10 ma%=020 IF INKEY(1)=0 THEN GOSUB 10030 IF INKEY(2)=0 THEN GOSUB 30040 IF INKEY(8)=0 THEN GOSUB 50050 IF INKEY(0)=0 THEN GOSUB 70060 GOTO 20100 ' right110 ma%=ma%+1: GOSUB 900: RETURN300 ' down310 ma%=ma%+40: GOSUB 900: RETURN500 ' left510 ma%=ABS(ma%Gate-1): GOSUB 900: RETURN700 ' up710 ma%=ABS(ma%-40): GOSUB 900: RETURN900 ' set R12 and R13910 l%=ma% AND 255: h%=&30 OR ((ma%\256) AND 3) :OUT &BC00,13:OUT &BD00,l%: OUT &BC00,12:OUT &BD00,h%930 RETURN</pre> Which looks like Array to the following: [[File:CRTC-Coarse-scrolldisplay.gif]] <br> === Advanced hardware scrolling === To achieve smoother hardware scrolling, other tricks are required in complement to R12/R13. Usually, R3 is used for smooth horizontal scroll and R5 for smooth vertical scroll. A good example of smooth hardware multidirectional scrolling game on CPC is [https://www.cpc-power.com/index.php?page=detail&num=2119 Super Cauldron], released in 1993. Everything you need to know about hardware scrolling on CPC The DISPTMG can be found [https://www.cpcwiki.eu/forum/programming/hardware-scrolling-21687/ there]. <br> == Split screen forced using R8 (aka RuptureDISPTMG Skew) == While there is usually 1 CRTC frame per screen frame, the screen frame can be divided into multiple CRTC frames of varying proportions. This is useful for defining different scrolling zones in your screen frame. For example, it was used for hardware parallax scrolling in the game [https://www.cpc-power.com/index.php?page=detail&num=1307 The Living Daylights], released in 1987. [https://www.cpcwiki.eu/forum/programming/the-living-daylights-extra-colours-in-mode-1-rasters-screen-splits/ Source] And this is basically the bread and butter of innumerable CPC demos. Some rules of thumb [https://www.cpcwiki.eu/forum/programming/advice-on-split-screen-code/msg242186/ Source]:* changes to the screen address have to be done anywhere in the previous split* changes to the height of the split have to be done inside the current split (after it has startedtype 0, in the area of the size of the previous split)* changes to screen mode 3 and colours are happening immediately CRTC registers and screen splitting:*reg 0 (63) = x-screenwidth (usually always 63)*reg 1 (50) = x-splitwidth (e.g.50)*reg 2 (51) = x-splitstart (e.g. 51)*reg 3 (08) = x-finestart (maybe use this for half-char scrolling)*reg 4 (##) or by setting R6= y-splitheight-1 (set this inside the current split)*reg 5 (00) = y-finestart*reg 6 (25) = y-max visible splitpart (same like 4)*reg 7 (##) = inside last split -> set to 0; inside first split, but after vblank -> set to 255*reg 9 (07) = y-lines/char-on type 1 Set this inside the previous split:*reg12 (##) = address high (char / 256 + block * 16)*reg13 (##) = address low (char mod 256) Total height of all splits must be 39. The [https://www.cpcwiki.eu/forum/programming/interrupt-positions-with-various-sized-screens/ IntPos tool] by Kevin Thacker can help visualize the potential split screen areas. Note: If all you want is multiple graphics modes in the same frame, you don't need to touch the CRTC at all. More information here: [https://www.cpc-power.com/cpcarchives/index.php?page=articles&num=184 Multi-Mode Graphique (FR)] <br> == CUDISP (aka CURSOR) == CUDISP (Cursor Display) signal defines the hardware cursor. CRTC pin CUDISP It is not connected possible to force the Gate Array, so it has no effect DISPTMG on a barebone CPC type 2 or Plus machine. However, this signal is provided to the [[Connector:Expansion port]]. And it is used by the [[PlayCity]] and [[Play2CPC]] expansions. <br> == DISPTMG (aka Display Enable) == DISPTMG (Display Timing) signal defines the border. When DISPTMG is "0" the border colour is output by the Gate Array to the display5.
The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.
While border is active, all the CRTC counters continue to increment normally == HSYNC and addresses continue to be generated.VSYNC ==
The DISPTMG signal is composited from its 3 internal subcomponents: HBORDER (Horizontal)On CPC, VBORDER (Vertical), SBORDER (Split) by using HSYNC and VSYNC from the NOR function. DISPTMG is "0" if at least one of its subcomponents is "1". These 3 subcomponents CRTC are all independent of each otherpassed into the Gate-Array.
<br>When HSYNC is active Gate-Array outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14us.
=== HBORDER ===The HSYNC is modified before being sent to the monitor. It happens 2us after the HSYNC from the CRTC and lasts 4us when HSYNC length is greater or equal to 6.
On all CRTCsIf R2=46, HBORDER and HSYNC width is disabled when HCC=0 14 then monitor hsync starts at 48 and enabled when HCC=R1lasts until 51.
The exception is for CRTC2 during an HSYNC: On a CPC monitor, the HCC=0 check HSYNC is skipped, so HBORDER stays onrendered in "absolute black". It is darker than the black output by the Gate-Array.
<br>The VSYNC is also modified before being sent to the monitor. It happens two lines* after the VSYNC from the CRTC and stay two lines (same cut rule if VSYNC is lower than 4). PAL (50Hz) does need two lines VSYNC_width, and 4us HSYNC_width.
=== VBORDER === On all CRTCsUsing CRTC1, VBORDER is disabled when VCC=0 and enabled when VCC=R6. On CRTCs 0/1/2, the condition VCC=R6 is tested on every cycle. On CRTCs 3/4, the condition VCC=R6 is tested only at each new character line start (when VLC=0 and HCC=0). <br> === SBORDER === Split border is a technique similar to split rasters, except that it is handled by the CRTC instead of the [[Gate Array]]. DISPTMG can be temporarily forced to 0 by using R8 (DISPTMG Skew) on CRTCs 0/3/4, or by setting R6=0 on CRTC 1. It is not possible to force DISPTMG on CRTC 2. <br> === Border bytes === Despite their 1MHz clock speed, CRTCs 0/2 have been observed to change state at a rate equivalent to 2MHz chips by responding to both the rising and falling edges of each clock cycle. ==== Interline border ====On CRTCs 0/2, R1>R0 generates one byte (0.5µs) of border at the end of the raster line. On CRTCs 1/3/4, it does not. If border skew is used, the border byte will skew and change into a full character-VSYNC width border instead. ==== Border conflict ====If R1=value 0 and HCC=0, we expect HBORDER to activate as HCC=R1 and we also expect HBORDER to deactivate as HCC=0. In this situation, all CRTCs activate HBORDER. If R6=0 and VCC=0, we expect VBORDER to activate as VCC=R6 and we also expect VBORDER to deactivate as VCC=0. In this situation, all CRTCs activate VBORDER. On CRTC 1, even SBORDER is activated. But on CRTCs 0/2, the first raster line shows an alternation of bytes of VBORDER and displayable characters. To see the border bytes with your own eyes, type this BASIC line after reset:<pre>BORDER 6:OUT &BC00,6:OUT &BD00,0</pre> <br> == HSYNC == The HSYNC signal from the CRTC is not directly connected to the display. It is passed to the [[Gate Array]] for further modification. See its wiki page. While HSYNC is active, all the CRTC counters continue to increment normally and addresses continue to be generated. On all CRTCs, while an HSYNC is ongoing, the condition HCC=R2 is ignored. So we cannot trigger means a new HSYNC during an HSYNC. === Contiguous HSYNCs === On CRTC 0, two HSYNCs cannot be contiguous. They are always separated by at least 1 CRTC character. What happens is that when HSC=R3 and HCC=R2, the condition HSC=R3 takes precedence over the condition HCC=R2 and HSYNC is stopped. On CRTCs 1/2/3/4, HSYNCs can be contiguous. === Signal delay === On all CRTCs, there is a 1µs delay in display between when the CRTC provides a video pointer, and when the Gate Array displays the corresponding 16-bit character. But on CRTCs 0/1/2, there is no delay for HSYNC. On CRTCs 3/4, the Amstrad engineers fixed the issue by adding a 1µs delay for the HSYNC signal to match the display signal. So now we have a bigger issue: on CRTCs 3/4, HSYNC occurs 1µs later than on CRTCs 0/1/2. Interrupts being dependent on HSYNC, this is a serious compatibility issue for time-sensitive code. It also explains why the CTM monitor has to be calibrated differently on CRTCs 3/4. Fortunately, the issue is easy to fix, by adjusting the HSYNC width with CRTC register 3. === Discolouration effect === On CRT monitors from other brands, a colour calibration can happen just after the C-HSYNC pulse. So even when a fully valid C-HSYNC pulse value of 4µs is emitted, an HSYNC shorter than usual combined with a coloured border can induce a discolouration effect on those monitors. === Screen wobbling and Fine horizontal hardware scroll === These effects use invalid HSYNC signals, which are poorly supported by modern displays. However, these effects were used in commercial-era CPC games, so it's fine if you choose to use them. When R2 increases by 1, the screen is shifted to the left by 16 mode2 pixels. When R2 decreases by 1, the screen is shifted to the right by 16 mode2 pixels. When R3l increases by 1 (and if <6), the screen is shifted to the left by 8 mode2 pixels. When R3l decreases by 1 (and if >2), the screen is shifted to the right by 8 mode2 pixels. The shift is not instantaneous but follows a logarithmic attenuation across several raster lines. This property can be used to get even finer horizontal control by modifying R2/R3 on each raster line. [[Longshot]] has demonstrated [https://youtu.be/1q7RQykZoKY horizontal hardware scroll] with one-pixel precision in mode1 on all CRTCs. However, because you have to synchronize with each line, it takes a lot of CPU time if it's done in fullscreen (272 lines). <br> == VSYNC == The VSYNC signal from the CRTC is not directly connected to the display. It is passed to the [[Gate Array]] for further modification. See its wiki page. While VSYNC is active, all the CRTC counters continue to increment normally and addresses continue to be generated. On all CRTCs, while a VSYNC is ongoing, the condition VCC=R7 is ignored. So we cannot trigger a new VSYNC during a VSYNC. On CRTCs 0/1/2, the sole condition to trigger a VSYNC is that VCC=R7. While on CRTCs 3/4, it is necessary to have VCC=R7 and HCC=0 and VLC=0 to trigger a VSYNC. === Blocked VSYNC === On CRTC 0, if R7 is modified with the value of VCC when HCC<2, we are in blocked VSYNC. Then, the VSYNC can no longer occur on VCC=R7 until an unblocking condition is produced (VCC or R7 update). Source: §16.4 "Conditions to consider" of the CRTC Compendium === Ghost VSYNC === On CRTC 2, if a VSYNC is triggered during an HSYNC, the CRTC produces a ghost VSYNC. The CRTC then counts the lines as if a VSYNC were taking place by preventing a new VSYNC from occurring, but without the VSYNC pin being enabled. === PPI VSYNC === The VSYNC pin of the CRTC is directly connected to bit0 of port B of the PPI. There is no delay involved. On Amstrad CPC (not Plus!), it is also possible to reverse the direction of PPI port B to output a "fake" VSYNC signal directly from the PPI to the Gate Array. As an exception, the Ghost VSYNC of CRTC 2 overpowers the Fake VSYNC. === Subpixel vertical hardware scroll === By tuning very precisely when the VSYNC signal is sent to the monitor, Longshot has demonstrated [https://youtu.be/bSjRU6Wye00 vertical hardware scroll] with a precision of 1/128th of a pixel. Furthermore, subpixel vertical scrolling consumes very little CPU. === Mid-VSYNC === On all CRTCs, in both interlace modes, a mid-VSYNC is generated when VCC=R7 on the even field. The VSYNC pulse starts in the middle of the raster line, at HCC=R0/2. As an exception, on CRTCs 3/4, if R7=0 then mid-VSYNC will instead occur on the odd field. Source: §19.7 "Mid-VSYNC" of the CRTC Compendium. <br> == Interlace modes == Note: Some details about the CRTC interlace implementations are missing in this article. Consider it as an introduction to the topic. [[File:CRTC Interlace modes.png]] For a CRTC character line with n raster lines, R9 must be set to n-1 on all CRTCs, regardless of the interlace settings. The exception is for CRTCs 0/3/4 in IVM mode, where R9 must be set to n-2. === Interlace sync mode (ISM) === In this mode, the same information is painted in both fields to enhance readability. Reprogramming the CRTC is not necessary. === Interlace sync and video mode (IVM) === In this mode, alternating lines are displayed in the even and odd field to double the resolution. On the even field, the CRTC displays the lines for which VLC is even. On the odd field, the CRTC displays the lines for which VLC is odd. It is necessary to reprogram the CRTC as if we were building a frame of 624 lines. CRTC 2 is the exception: R4, R5, R6, R7 do not need to be reprogrammed as it considers each character line to be a double character line. === Interlace adjustment line === On all CRTCs, in both interlace modes, an additional line (the 625th line) is added automatically by the CRTC at the end of the even field. This line is added after the lines of the vertical adjustment mode. <br>
== CRTC registers The 6845 Registers ==
The Internal registers of the 6845 are:
{| class="wikitable"{{Prettytable|width: 700px; font-size: 2em;}}|''Register Index''||''Register Name''||''Range''||''CPC Setting''||''Notes''
|-
!rowspan=2|Register Index!rowspan=20|Register Name!colspan=3|Read/Write!rowspan=2Horizontal Total|Range!rowspan=2|CPC Setting!rowspan00000000||63||Width of the screen, in characters. Should always be 63 (64 characters). 1 character =2|Notes= 1µs.
|-
!CRTC 0!CRTCs |1/2!CRTCs 3/4||Horizontal Displayed||00000000||40||Number of characters displayed. Once horizontal character count (HCC) matches this value, DISPTMG is set to 1.
|-
|02||Horizontal Total (-1)||colspan=3 style="text-align: center;"|WriteSync Position||00000000||6346||Width of When to start the screen, in characters. Should always be 63 (64 characters). 1 character == 1μsHSync signal.
|-
|13||Horizontal Displayedand Vertical Sync Widths||colspan=3 style="text-align: center;"VVVVHHHH|Write|128+14|00000000||40||Number of HSync pulse width in characters displayed. Once horizontal character count (HCC0 means 16 on some CRTC) matches this value, DISPTMG is set to 1should always be more than 8; VSync width in scan-lines.(0 means 16 on some CRTC. Not present on all CRTCs, fixed to 16 lines on these)
|-
|24||Horizontal Sync PositionVertical Total||colspan=3 style="text-align: center;"x0000000|Write|38|00000000||46||When to start Height of the HSync signalscreen, in characters.
|-
|35||Horizontal and Vertical Sync WidthsTotal Adjust||colspan=3 style="text-align: center;"xxx00000|Write|0|VVVVHHHH||128+14||VSync width Measured in scan-lines (Not present on all CRTCsscanlines, fixed to 16 lines can be used for smooth vertical scrolling on these) ; HSync pulse width in charactersCPC.
|-
|46||Vertical Total (-1)||colspan=3 style="text-align: center;"|WriteDisplayed||x0000000||3825||Height of the displayed screen, in characters. Once vertical character count (VCC) matches this value, DISPTMG is set to 1.
|-
|57||Vertical Total AdjustSync position||colspan=3 style="text-align: center;"x0000000|Write|30|xxx00000||0||Measured When to start the VSync signal, in scanlines, can be used for smooth vertical scrolling on CPCcharacters.
|-
|68||Vertical DisplayedInterlace and Skew||colspan=3 style="text-align: center;"xxxxxx00|Write|0|x0000000||25||Height of displayed screen in characters. Once vertical character count (VCC) matches this value, DISPTMG is set to 1.00: No interlace; 01: Interlace Sync Raster Scan Mode; 10: No Interlace; 11: Interlace Sync and Video Raster Scan Mode
|-
|79||Vertical Sync PositionMaximum Raster Address||colspan=3 style="text-align: center;"xxx00000|Write|7|x0000000||30||When to start the VSync signalMaximum scan line address on CPC can hold between 0 and 7, in characters.higher values' upper bits are ignored
|-
|810||Interlace and SkewCursor Start Raster||colspan=3 style="text-align: center;"|Write||CCDDxxIIxBP00000||0||CC: Cursor Skew (Only in CRTCs 0, 3 and 4)not used on CPC. DD: Display Skew B = Blink On/Off; P = Blink Period Control (Only in CRTCs 0, 3 and 4Slow/Fast). II: Interlace ModeSets first raster row of character that cursor is on to invert.
|-
|911||Maximum Cursor End Raster Address (aka Number of Scan Lines) (-1)||colspan=3 style="text-align: center;"|Write||xxx00000||70||Maximum scan line address Sets last raster row of character that cursor is on CPC can hold between 0 and 7, higher values' upper bits are ignored.to invert
|-
|1012||Cursor Display Start RasterAddress (High)||style="text-align: center;"xx000000|Write||style="text-align: center;"|Write||Read/Write||xBP00000||0||B = Blink On/Off; P = Blink Period Control (16 or 32 frames). Sets first raster row of character that cursor is on to invert.48
|-
|1113||Cursor End RasterDisplay Start Address (Low)||style="text-align: center;"|Write||style="text-align: center;"|Write||Read/Write||xxx0000000000000||0||Sets last raster row Allows you to offset the start of character that cursor is on to invertscreen memory for hardware scrolling, and if using memory from address &0000 with the firmware.
|-
|1214||Display Start Cursor Address (High)||Read/Write||style="text-align: center;"|Write||Read/Write||xx000000||48||On Amstrad Plus, bit7 of the printer port is controlled by bit3 of CRTC R12 (ie. bit11 of Display Start Address).0
|-
|1315||Display Start Cursor Address (Low)||Read/Write||style="text-align: center;"|Write||Read/Write||00000000||0||Allows you to offset the start of screen memory for hardware scrolling, and if using memory from address &0000 with the firmware.
|-
|1416||Cursor Light Pen Address (High)||colspan=3 style="text-align: center;"|Read/Write||xx000000||0||Read Only
|-
|15||Cursor Address (Low)||colspan=3 style="text-align: center;"|Read/Write||00000000||0|||-|16||Light Pen Address (High)||colspan=3 style="text-align: center;"|Read||xx000000||||On CRTC1, bit6 of Status register goes to 0 when R16 is read.|-|17||Light Pen Address (Low)||colspan=3 style="text-align: center;"|Read||00000000||||On CRTC1, bit6 of Status register goes to 0 when R17 is read.Read Only
|-
|}
<br>registers 18-31 read as 0, on type 0 and 2.registers 18-30 read as 0 on type1, register 31 reads as 0x0ff.
=== Screen size ===Details about Reg. 12 and Reg. 13 specifically:
We can calculate the screen size in words by multiplying R1 x R6 x .------- REG 12 --------. .------- REG 13 --------. | | | | 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 .--.--.--.--.--.--.--.--. .--.--.--.--.--.--.--.--. |X |X | | | | | | | | | | | | | | | | '--'--'--'--'--'--'--'--' '--'--'--'--'--'--'--'--' '--.--'--.--'---------------.-----------------' | | | | | '------> Offset for setting | | videoram | | (R9+11024 positions) | | Bits 0. And then multiplying the result by 2 to have the screen size in bytes.9 | |With the default CRTC values, we obtain 40 x 25 x | '-------------------------> Video Buffer : note (7+1) x 2 = 16000 bytes. |So we can observe that only part of the 16384 bytes '-------------------------------> Video Page : note (=16KB2) page of VRAM is actually displayed on screen note (1) note (2) .--.--.--------------. .--.--.---------------. |11|10| Video Buffer | |13|12| Video Page |<br> |--|--|--------------| |--|--|---------------| | 0| 0| 16Ko | | 0| 0| 0000 - 3FFF | |--|--|--------------| |--|--|---------------| | 0| 1| 16Ko | | 0| 1| 4000 - 7FFF | |--|--|--------------| |--|--|---------------| | 1| 0| 16Ko | | 1| 0| 8000 - BFFF | |--|--|--------------| |--|--|---------------| | 1| 1| 32Ko | | 1| 1| C000 - FFFF | '--'--'--------------' '--'--'---------------'
=== So, it's possible to use 32KB screen size (used for [[Programming:Overscan|overscan]]) by setting bits 11 and 10 both to 1 (of Register 12). Bits MA11 and MA10 of the address generated by the CRTC are not written on the address bus to access ===video memory; settings both bits to 1 is the only way to cause a carry to bit MA12 when address pass over the end of current video page to change the memory address to the next video page.
On CRTCs 0/1/2, if a Write Only register is read from, "0" is returned. The register accessing scheme on CRTCs 3/4 makes it impossible to happen.== CRTC Differences ==
On In this section I will attempt to identify all CRTCs, only the 5 least significant bits of the selected register number are considered to write to a register. The other bits are ignoreddifferences between each CRTC.
On CRTCs 0/1/2, only The following tables list the 5 least significant bits of the selected register number are considered to read a registerfunctions that can be accessed for each type:* On CRTCs 0/2, registers 18-31 read as 0* On CRTC 1, registers 18-30 read as 0, register 31 reads as &FF
On CRTCs 3/4, only the 3 least significant bits of the selected register number are considered to read a register, according to the following table:Type 0
{| class="wikitable"{{Prettytable|width: 700px; font-size: 2em;}}!Nb!Register!Definition|''b1''||''b0''||''Function''||''Read/Write''
|-
|0||R160||Light Pen Address (High)Select internal 6845 register||Write Only
|-
|0||1||R17Write to selected internal 6845 register||Light Pen Address (Low)Write Only
|-
|21||R100||Cursor Start Raster-||-
|-
|31||R111||Cursor End RasterRead from selected internal 6845 register||Read only
|-
|4} Type 1 {|{{Prettytable|R12width: 700px; font-size: 2em;}}|''b1''|Display Start Address (High)|''b0''||''Function''||''Read/Write''
|-
|50||R130||Display Start Address (Low)Select internal 6845 register||Write Only
|-
|60||R141||Cursor Address (High)Write to selected internal 6845 register||Write Only
|-
|71||R150||Cursor Address (Low)Read Status Register||Read Only |-|1||1||Read from selected internal 6845 register||Read only
|}
<br>Type 2
== CRTC register differences == CRTC types 3 and 4 are identical in every way, except for the unlocking mechanism, split screen, hardware soft scroll and 8-bit printer port functionalities specific to the [[ASIC]]. <br> === R10/R11 on ASIC/Pre-ASIC === The cursor raster registers R10/R11 act as status registers when read on CRTCs 3/4. They behave as normal cursor raster registers upon write. {| class="wikitable"! R10 {{Prettytable|width: 700px; font- Bit numbersize: 2em;}}! Bit value! Event|''b1''||''b0''||''Function''||''Read/Write''
|-
|0|1|C0=R00||Select internal 6845 register||Write Only
|-
|0||1|0|C0=R0/2Write to selected internal 6845 register||Write Only
|-
|21||0|C0=R1|-||-1 (if R0>=R1)
|-
|31|0|C0=R21||Read from selected internal 6845 register||Read only
|-
|} Type 3 and 4 {|0{{Prettytable|width: 700px; font-size: 2em;}}|C0=R2+R3''b1''||''b0''||''Function''||''Read/Write''
|-
|5|01|R3h>|0 : C0=0..R0 on the line R3h from Vsync (C4=R7)R3h=0 : C0=0..R0 over 15 lines from Vsync (C4=R7)||Select internal 6845 register||Write Only
|-
|60||1||Write to selected internal 6845 register||Write Only |-|1||0||Read from selected internal 6845 register||Read Only |-|Always 1||1||Read from selected internal 6845 register||Read only
|-
|7
|0
0
|C0=0..R0-1 : VMA.Lsb=0xFF
C0=R0 : VMA'.Lsb=0x00 (same cond if C0=R0=0)
|}
It is not possible to read from all the internal registers, this table shows the read/write status of each register for each type: {| class="wikitable"! R11 {{Prettytable|width: 700px; font- Bit numbersize: 2em;}}! Bit value! Event|rowspan=2|''Register Index''||rowspan=2|''Register Name''||colspan=4|''Type''
|-
|0|0|C4=R4 and C9=R9 and C0=R0 : Last char of screen1||2||3||4
|-
|1|0|C4=R6-1 and C9=R9 and C0=R0 : Last char displayed|Horizontal Total||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|1||Horizontal Displayed||Write Only||Write Only||Write Only||(note 2)|0|C4=R7-1 and C9=R9 and C0=R0 : Last char before Vsync(note 3)
|-
|32|0/1|Timer 16 CRTC framesHorizontal Sync Position||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|43|1|Always 1Horizontal and Vertical Sync Widths||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|54|0|C9=R9 : C0=0 to R0Vertical Total||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|65|0|Always 0Vertical Total Adjust||Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|76|1|(C9=R9 and C0=R0) or (C9=0 and C0=0 to R0-1)Vertical Displayed||Write Only||Write Only||Write Only||} <br> === Horizontal and Vertical Sync (R3) === Type 0:*Bits 7..4 define Vertical Sync Width. If 0 is programmed, this gives 16 lines of VSYNC.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, no HSYNC is generated (and therefore, no interrupts). Type 1:*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, no HSYNC is generated (and therefore, no interrupts). Type note 2:*Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, this gives a HSYNC width of 16. Types 3/4:*Bits 7..4 define Vertical Sync Width. If 0 is programmed, this gives 16 lines of VSYNC.*Bits 3..0 define Horizontal Sync Width. If 0 is programmed, this gives a HSYNC width of 16. <br> === Interlace and Skew (R8) === Types 0/3/4:*Bits 7..6 define the skew ||(delay) of the CUDISP signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).*Bits 5..4 define the skew (delay) of the DISPTMG signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).*Bits note 3..2 are ignored.*Bits 1..0 define the interlace mode (00 = No Interlace ; 01 = Interlace Sync ; 10 = No Interlace ; 11 = Interlace Sync and Video). Types 1/2:*Bits 7..2 are ignored.*Bits 1..0 define the interlace mode. <br> === R31 on Type 1 === R31 is described in the UM6845R documentation as "Dummy Register". Its use is described in the documentation for the Rockwell R6545 in combination with R18, R19 and R8 and the Status Register. In the UM6845R it appears to have no effect. Reading and writing does nothing. Reading it returns &FF. R31 doesn't exist on CRTCs 0/2/3/4. <br> === Status register on Type 1 === The UM6845R has a status register that can be read using port &BExx. Bit 6 is set to 1 if there is a strobe input to the /LPEN signal. It is cleared to 0 when either R17 or R16 (LPEN address) of the CRTC are read. It signals there is a valid LPEN input. On Kevin Thacker's CPC with UM6845R, it is triggered at power on, R17 and R16 have the values 0 when read. Bit 5 is set to 1 when CRTC is in "vertical blanking". Vertical blanking is when the vertical border is active. i.e. VCC>=R6. It is cleared when the frame is started (VCC=0). It is not directly related to the DISPTMG output (used by the CPC to display the border colour) because that output is a combination of horizontal and vertical blanking.This bit will be 0 when pixels are being displayed. All the other bits read as 0 and don't have any function. <br> == CRTC Type Detection == It is possible to detect the CRTC Type using software methods, and this is done to: * warn that the software was not designed for the detected 6845 and may function incorrectly* to adapt the software so that it will run with the detected 6845 * In most cases, the type of the detected 6845 is reported Detection routine in BASIC:<pre>10 MODE 1:' Reinitialize screen20 OUT &BC00,31:IF INP(&BF00)=255 THEN PRINT"crtc 1":END30 OUT &BC00,12:IF INP(&BF00)=0 THEN PRINT"crtc 2":END40 OUT &BC00,20:IF INP(&BF00)=0 THEN PRINT"crtc 0":END50 PRINT"crtc 3/4"</pre> Distinguishing between CRTCs 3 and 4 can be done by trying to [[Programming:Unlocking ASIC|unlock the ASIC]] or by testing the [[8255|PPI chip]]. On ASIC, if PPI Port B is set as output it will behave the same as input. <br> == CRTC Timing Diagrams ==[[File:CRTC Timing Diagram Rockwell.png]] <br> [[File:CRTC timing small.gif]] <br> == Internal Counters == {| class="wikitable"! Counter name! Abbr! Alternate name! Compared with! Comment
|-
|Horizontal Character Counter7|HCC|C0Vertical Sync position|R0, R1, R2| Increments on every clock cycleWrite Only||Write Only||Write Only||(note 2)||(note 3)
|-
|Horizontal Sync Counter8|HSC|C3lInterlace and Skew|R3l|Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|Vertical Character Counter9|VCC|C4Maximum Raster Address|R4, R6, R7|Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|Vertical Sync Counter10|VSC|C3hCursor Start Raster|R3h|R3h is fixed to 0 on CRTCs 1/Write Only||Write Only||Write Only||(note 2. This gives 16 lines of VSYNC)||(note 3)
|-
|Vertical Line Counter11|VLC|C9Cursor End Raster|R9, R10, R11|If not in IVM mode, this counter is exposed on CRTC pins RA0..RA4Write Only||Write Only||Write Only||(note 2)||(note 3)
|-
|Vertical Total Adjust Counter12|VTAC|C5Display Start Address (High)|R5|This counter does not exist on CRTCs 0Read/3Write||Write Only||Write Only||Read/4. C9 is reused insteadWrite (note 2)||(note 3)
|-
|Frame Counter13||Display Start Address (Low)||Read/Write||Write Only||Write Only||Read/Write (note 2)||(note 3) |FC-|14||Cursor Address (High)||Read/Write||Read/Write||Read/Write||Read/Write (note 2)||(note 3)|-|Used to alternate frames in interlace and for CRTC cursor blinking15||Cursor Address (Low)||Read/Write||Read/Write||Read/Write||Read/Write (note 2)||(note 3)|-|16||Light Pen Address (High)||Read Only||Read Only||Read Only||Read Only (note 2)||(note 3)|-|17||Light Pen Address (Low)||Read Only||Read Only||Read Only||Read Only (note 2)||(note 3)
|-
|Memory Address
|MA
|
|R14/R15
|This counter is exposed on CRTC pins MA0..MA13
|}
When IVM mode is activated, VLC continues to increment normally. However, RA is not identical to VLC anymore. Instead, VLC is considered shifted left by 1 bit, and bit0 represents the parity of the field (even/odd).'''Notes'''
<br>1. On type 0 and 1, if a Write Only register is read from, "0" is returned.
== CRTC counter differences ==2. See the document "Extra CPC Plus Hardware Information" for more details.
=== MA buffering ===3. CRTC type 4 is the same as CRTC type 3. The registers also repeat as they do on the type 3.
No matter its type, the CRTC never buffers any of its counters, except for the video pointer MA. The buffer MA' is needed because MA has to be reloaded at the beginning of every raster line.== Horizontal and Vertical Sync (R3) ==
At the end of the display of the last raster line of each character line (ie. when HCC=R1 and VLC=R9), MA' captures the current value of MA.UM6845:
CRTC 2 Bits 7..4 define Vertical Sync Width. If 0 is the exception: at the end programmed this gives 16 lines of the display of the last raster line of the frame, MA' captures R12/R13 instead of MAVSYNC.Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
<br>UM6845R:
=== MA reload ===Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated.
On CRTCs 0/3/4, at the beginning of the first raster line of the frame, MA and MA' are loaded with R12/R13. Otherwise, MA is loaded with MA'.MC6845:
On CRTC 2, Bits 7..4 are ignored. Vertical Sync is fixed at the beginning of every raster line of the frame (including the first one), MA 16 lines.Bits 3..0 define Horizontal Sync Width. If 0 is loaded with MA'programmed this gives a HSYNC width of 16.
On CRTC 1, at the beginning of every raster line of the first character line of the frame (ie. when VCC=0), MA is loaded with R12Pre-ASIC/R13 instead of MA'. '''This is a major source of incompatibility if the programmer does not take care.''' In demos and games, to be compatible with all CRTCs, program R12/R13 only when VCC≠0. This will then take effect at the next CRTC frame start.ASIC:
==== Rupture For Dummies (R5 bug) ====Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.
CRTC 1 has a bug that occurs when R5 is updated with a non-zero value when HCC=R0 = UM6845R and VLC≠R9, but only when R5 was previously 0. This changes the MA update source to R12/R13 instead of MA'. The CRTC then loads R12/R13 into MA at the beginning of every scanline, regardless of the VCC value.R31 ==
This R5 bug also messes with the frame parity management. However, it R31 is possible to fix the parity of the frame by activating/deactivating described in the IVM interlace modeUM6845R documentation as "Dummy Register".
The vertical adjustment operates normally after Its use is described in the RFD is triggered. If vertical adjustment is not neededdocumentation for the Rockwell R6545 in combination with R18, R5 can be reset at any time after R19 and R8 and the RFD is activatedStatus Register.
This In the UM6845R it appears to have no effect is used in the [https://www.cpc-power.com/indexReading and writing does nothing.php?page=detail&num=19308 DSC4 demo]Reading it returns 0x0ff.
<br>R31 doesn't exist on types 0,2,3.
=== VSC (C3h) overflow =UM6845R and R12/R13 ==
During a VSYNC on CRTCs 0/3/4, if VSYNC Width (R3h) is changed with a value less than the current VSC, then VSC overflows and will count up The UM6845R differs to its maximum value (15) before looping back and counting up again until it reaches the new value other CRTC in respect of R3hR12/R13.
On CRTCs 1When VCC=0, R12/2, R13 is re-read at the VSYNC width is fixed to 16 charactersstart of each line. It is not possible to modify it. Therefore, VSC cannot R12/R13 can therefore be overflowedchanged for each scanline when VCC=0.
<br>Just like other CRTCs when RC==(R9-1), the current MA is captured for the next char-line.
In demos to make a display compatible with all CRTCs program R12/R13 when VCC!=== HSC (C3l) overflow ===0. This will then take effect at the next frame start.
During an HSYNC, if HSYNC Width (R3l) is changed with a value less than the current HSC, then HSC overflows and will count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3l.== UM6845R status register ==
The only exception is for CRTC 1 with UM6845R has a value of 0, which immediately cancels the current HSYNCstatus register that can be read using port &BExx.
<br>Bit 6 is set to 1 if there is a strobe input to the /LPEN signal. It is cleared to 0 when either R17 or R16 (LPEN address) of the CRTC are read. It signals there is a valid LPEN input. On my CPC (arnoldemu) with UM6845R, it is triggered at power on, R17 and R16 have the values 0 when read.
=== Bit 5 is set to 1 when CRTC is in "vertical blanking". Vertical blanking is when the vertical border is active. i.e. VCC (C4) overflow ==>=R6.
On all CRTCs, if Vertical Total It is cleared when the frame is started (R4VCC=0) . It is changed with a value less than VCC, then:* if this update was done when VCC < R4, then VCC overflows and will count up not directly related to its maximum value the DISPTMG output (127) before looping back and counting up again until it reaches used by the new value of R4* if this update was done when VCC = R4, the current character line was already decided CPC to be display the last one border colour) because that output is a combination of the current framehorizontal and vertical blanking. No update to R4 This bit will make the CRTC change its mind for the current framebe 0 when pixels are being displayed.
The only exception when VCC = R4 is for CRTC 1 with a value of 0, which will cause VCC to overflow. <br> === HCC (C0) overflow === If Horizontal Total (R0) is changed with a value less than All the current HCC, then:* on CRTCs other bits read as 0/1/2, HCC overflows and will count up to its maximum value (255) before looping back and counting up again until it reaches the new value of R0* on CRTCs 3/4, the current line is considered finished and HCC is immediately reset to 0 on the next line <br> === VLC (C9) overflow === If Number of Scan Lines (R9) is changed with a value less than the current VLC, then:* on CRTCs 0/1/2, VLC overflows and will count up to its maximum value (31) before looping back and counting up again until it reaches the new value of R9* on CRTCs 3/4, the current line is considered the last one of this CRTC character and VLC will reset to 0 on the next line As an exception, on CRTCs 0/2, if VLC is modified during the last frame line, then the updated value will not be considered for the current frame. <br> === VTAC (C5/C9) overflow === During vertical adjustment mode, if Vertical Total Adjust (R5) is changed with a value less than the current VTAC, then:* on CRTCs 0/1/2, VTAC overflows and will count up to its maximum value (31) before looping back and counting up again until it reaches the new value of R5* on CRTCs 3/4, the current line is considered the last one of the current frame and vertical adjustment will end As an exception, on CRTCs 0/2, if VTAC is modified during the last frame line, then the updated value will not be considered for the current frame. <br> === Vertical Adjustment mode === On CRTCs 3/4, this mode does not increment VCC, so VCC remains equal to R4. On CRTC 0, this mode increments VCC, causing it to exceed R4, but this increment occurs only once. On CRTCs 1/2, this mode increments VCC, causing it to exceed R4, and this increment can happen multiple times depending on the values of R5 and R9. Also, only CRTCs 1/2 don't have a dedicated C5 counter. On CRTCs 0/3/4, during Vertical Adjustment, C9 has to fullfil the VTAC role which means that it cannot fullfil its VLC role. This impacts address generation as R9 is not considered anymore. <br> === Counter freezes === On CRTCs 1/2/3/4, R0 accepts all values without causing any problems for counters. On CRTC 0:* Setting R0 to 0 will cause numerous issues that stem from the fact that VLC is frozen. As HCC never reaches 1, the logic that increments VLC is never triggered.* The logic that triggers vertical adjustment is broken if R0<2. <br> == Block Diagrams == {| class="wikitable"|-!Hitachi!UMC!Motorola|-|[[File:CRTC Block Diagram.png|Hitachi]]|[[File:UMC CRTC Block Diagram.png|UMC]]|[[File:Motorola CRTC Block Diagram.png|Motorola]]|} <br> == CRTC-II (aka Type 5) == The [[Media:CRTC-5-HD6345.pdf|HD6345 datasheet]] states it is upward-compatible with the HD6845S in pin and software. This chip was never used by Amstrad. However, some CPC enthusiasts have replaced the original CRTC chip in their CPC with this one. With this chip, split-screen becomes easy: [https://thecheshirec.at/2024/05/20/des-splitscreens-en-basic-sur-crtc5/ Split-screen in BASIC]. And 3 new graphics modes (160x100x16c, 320x100x4c, 640x100x2c) are available: [https://thecheshirec.at/2024/11/10/trois-nouveaux-modes-video-grace-au-crtc-5/ New graphics modes in BASIC]. This is the cheapest way to upgrade the CPC's graphics capabilities, costing only 1.29€. [https://thecheshirecfunction.at/2024/05/19/des-crtc5-a-129e/ Source] <br> == Datasheets ==
==== Used by Amstrad ====
* [https://thecheshirec.at/tag/crtc6845/ Leçons CRTC (CheshireCat)]
* [https://martin.hinner.info/vga/pal.html PAL video timing specification]
<br>
==Related pages==